MPC180 查看數據表（PDF） - Motorola => Freescale

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MPC180

MPC180 Security Processor

Motorola => Freescale 

resides in the memory map of the processor; therefore, when an application requires cryptographic

functions, it reads and writes to the appropriate memory location in the security processor.

EEPROM

MPC180

MPC860

System Bus

I/O or Network

Interface

SDRAM

Figure 4-1. MPC8xx System Example

EEPROM

MPC180

60x Bus

MPC8260

Local Bus

SDRAM

DIMMs

SDRAM

I/O or Network

Interface

SDRAM

Figure 4-2. MPC826x System Example

5 Architectural Overview

The MPC180 has a slave interface to the MPC8xx system bus and MPC8260 local bus and maps into the

host processor’s memory space. Each encryption algorithm is mapped to a unique address space. To perform

encryption operations, the host reads and writes to the MPC180 to setup the execution unit and, then,

transfers data to the execution unit directly or through the external bus interface.

In FIFO mode, the MPC180 accepts data into the 4-Kbit input buffer and returns burst data through the

output buffer. In this way, the host can automatically transfer bulk data through a given EU. This minimizes

host management overhead and increases overall system throughput. Once the host configures the external

bus interface (EBI), it receives an interrupt only after all data has been transferred or processed by the

MPC180.

MOTOROLA

MPC180 Security Processor Technical Summary

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