SC667201MMG3 查看數據表（PDF） - Freescale Semiconductor

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SC667201MMG3

Qorivva MPC5642A Microcontroller Data Sheet

Freescale Semiconductor 

Introduction

Table 2. MPC5642A series block summary

Block

Boot assist module (BAM)

Calibration bus interface

Controller area network (FlexCAN)

Crossbar switch (XBAR)

Cyclic redundancy check (CRC)

Deserial serial peripheral interface (DSPI)

e200z4 core

Enhanced direct memory access (eDMA)

Enhanced modular input-output system

(eMIOS)

Enhanced queued analog-to-digital

converter (eQADC)

Enhanced serial communication interface

(eSCI)

Enhanced time processor unit (eTPU2)

Error Correction Status Module (ECSM)

Flash memory

FlexRay

Frequency-modulated phase-locked loop

(FMPLL)

Interrupt controller (INTC)

JTAG controller

Memory protection unit (MPU)

Nexus port controller (NPC)

Periodic interrupt timer (PIT)

Reaction Module (REACM)

Function

Block of read-only memory containing executable code that searches

for user-supplied boot code and, if none is found, executes the BAM

boot code resident in device ROM

Transfers data across the crossbar switch to/from peripherals attached

to the calibration system connector

Supports the standard CAN communications protocol

Internal busmaster

CRC checksum generator

Provides a synchronous serial interface for communication with

external devices

Executes programs and interrupt handlers

Performs complex data movements with minimal intervention from the

core.

Provides the functionality to generate or measure events

Provides accurate and fast conversions for a wide range of

applications

Provides asynchronous serial communication capability with

peripheral devices and other microcontroller units

Second-generation co-processor processes real-time input events,

performs output waveform generation, and accesses shared data

without host intervention

The Error Correction Status Module supports a number of

miscellaneous control functions for the platform, and includes registers

for capturing information on platform memory errors if error-correcting

codes (ECC) are implemented

Provides storage for program code, constants, and variables

Provides high-speed distributed control for advanced automotive

applications

Generates high-speed system clocks and supports programmable

frequency modulation

Provides priority-based preemptive scheduling of interrupt requests

Provides the means to test chip functionality and connectivity while

remaining transparent to system logic when not in test mode

Provides hardware access control for all memory references

generated

Provides real-time development support capabilities in compliance

with the IEEE-ISTO 5001-2010 standard

Produces periodic interrupts and triggers

Works in conjunction with the eQADC and eTPU2 to increase system

performance by removing the CPU from the current control loop.

MPC5642A Microcontroller Data Sheet, Rev. 3.1

Freescale Semiconductor

7

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