MPC7410(2010) 查看數據表（PDF） - Freescale Semiconductor
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MPC7410
(Rev.:2010)
(Rev.:2010)
Freescale Semiconductor
MPC7410 Datasheet PDF : 6 Pages
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Voltage to the L2 I/Os and processor interface I/Os are provided through separate sets of supply pins and
may be provided at the voltages shown in Table B.
Table B. Input Threshold Voltage Setting
BVSEL Signal 3
Processor Bus Input
Threshold is Relative to:
L2VSEL Signal 3
L2 Bus Input Threshold is
Relative to:
Note
0
1.8 V
0
1.8 V
1
HRESET
2.5 V
HRESET
2.5 V
1, 2
1
Not Supported
1
2.5 V
1, 4, 5
HRESET
Not Supported
HRESET
Not Supported
—
Notes:
1. Caution: The input threshold selection must agree with the OVdd/L2OVdd voltages supplied.
2. To select the 2.5-V threshold option, BVSEL and/or L2VSEL should be tied to HRESET so that the two signals change state
together. This is the preferred method for selecting this mode of operation.
3. To overcome the internal pull-up resistance, a pull-down resistance less than 250 ohms should be used.
4. Default voltage setting if left unconnected (internal pulled-up).
5. Caution: The MPC7410TRXnnnNE does not support the default OVdd setting of 3.3 V. The BVSEL input must be tie either
low or to HRESET.
Table C. Recommended Operating Conditions
Characteristic
Core supply voltage
PLL supply voltage
L2 DLL supply voltage
Processor bus supply voltage
BVSEL = 0
BVSEL = HRESET
L2 bus supply voltage
BVSEL = HRESET
or BVSEL = 1
L2VSEL = 0
Input voltage
L2VSEL = HRESET
or L2VSEL = 1
Processor bus and
JTAG Signals
L2 Bus
Die-junction temperature
Symbol
Vdd
AVdd
L2AVdd
OVdd
OVdd
OVdd
L2OVdd
L2OVdd
Vin
Vin
Tj
Recommended Value
Unit
1.5V ± 50mV
V
1.5V ± 50mV
V
1.5V ± 50mV
V
1.8V ± 100mV
V
2.5V ± 100mV
V
Not Supported
V
1.8V ± 100mV
V
2.5V ± 100mV
V
GND to OVdd
V
GND to L2OVdd
V
-40 to 105
°C
MPC7410 RISC Microprocessor Hardware Specifications Addendum for the MPC7410TxxnnnNE Series, Rev. 2
Freescale Semiconductor
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