MPC8540(2004) 查看數據表（PDF） - Freescale Semiconductor
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MPC8540 Datasheet PDF : 1302 Pages
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Contents
Paragraph
Number
Title
Page
Number
9.5.11
9.5.12
9.6
9.6.1
Error Checking and Correcting (ECC) ...................................................................... 9-46
Error Management ..................................................................................................... 9-48
Initialization/Application Information ........................................................................... 9-49
DDR SDRAM Initialization Sequence ...................................................................... 9-50
10.1
10.1.1
10.1.2
10.1.3
10.1.4
10.1.4.1
10.1.4.2
10.1.5
10.1.5.1
10.1.5.2
10.2
10.2.1
10.2.2
10.3
10.3.1
10.3.1.1
10.3.1.2
10.3.1.3
10.3.1.4
10.3.1.5
10.3.1.6
10.3.2
10.3.2.1
10.3.2.2
10.3.2.3
10.3.2.4
10.3.2.5
10.3.2.6
10.3.3
10.3.3.1
10.3.3.2
10.3.3.3
Chapter 10
Programmable Interrupt Controller
Introduction.................................................................................................................... 10-1
Overview.................................................................................................................... 10-2
Features...................................................................................................................... 10-3
Interrupts to the Processor Core................................................................................. 10-4
Modes of Operation ................................................................................................... 10-5
Mixed Mode (GCR[M] = 1) .................................................................................. 10-5
Pass-Through Mode (GCR[M] = 0) ...................................................................... 10-6
Interrupt Sources........................................................................................................ 10-6
Interrupt Routing—Mixed Mode........................................................................... 10-7
Internal Interrupt Sources ...................................................................................... 10-7
External Signal Descriptions ......................................................................................... 10-8
Signal Overview ........................................................................................................ 10-8
Detailed Signal Descriptions ..................................................................................... 10-8
Memory Map/Register Definition ................................................................................. 10-9
Global Registers....................................................................................................... 10-16
Feature Reporting Register (FRR)....................................................................... 10-16
Global Configuration Register (GCR)................................................................. 10-17
Vendor Identification Register (VIR) .................................................................. 10-17
Processor Initialization Register (PIR) ................................................................ 10-18
IPI Vector/Priority Registers (IPIVPRn) ............................................................. 10-19
Spurious Vector Register (SVR).......................................................................... 10-19
Global Timer Registers ............................................................................................ 10-20
Timer Frequency Reporting Register (TFRR)..................................................... 10-20
Global Timer Current Count Registers (GTCCRn) ............................................. 10-21
Global Timer Base Count Registers (GTBCRn) ................................................. 10-21
Global Timer Vector/Priority Registers (GTVPRn) ............................................ 10-22
Global Timer Destination Registers (GTDRn) .................................................... 10-23
Timer Control Register (TCR)............................................................................. 10-24
IRQ_OUT and Critical Interrupt Summary Registers ............................................. 10-26
IRQ_OUT Summary Register 0 (IRQSR0) ......................................................... 10-26
IRQ_OUT Summary Register 1 (IRQSR1) ......................................................... 10-27
Critical Interrupt Summary Register 0 (CISR0).................................................. 10-27
MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1
Freescale Semiconductor
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