MPC8540(2004) 查看數據表（PDF） - Freescale Semiconductor
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MPC8540 Datasheet PDF : 1302 Pages
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Contents
Paragraph
Number
Title
Page
Number
11.1
11.1.1
11.1.2
11.1.3
11.2
11.2.1
11.2.2
11.3
11.3.1
11.3.1.1
11.3.1.2
11.3.1.3
11.3.1.4
11.3.1.5
11.3.1.6
11.4
11.4.1
11.4.1.1
11.4.1.2
11.4.1.3
11.4.1.4
11.4.1.5
11.4.1.5.1
11.4.1.5.2
11.4.1.6
11.4.2
11.4.2.1
11.4.3
11.4.4
11.4.4.1
11.4.4.2
11.4.4.2.1
11.4.4.2.2
11.4.4.3
11.4.5
11.4.5.1
11.4.5.2
11.5
11.5.1
11.5.2
Introduction.................................................................................................................... 11-1
Overview.................................................................................................................... 11-2
Features...................................................................................................................... 11-2
Modes of Operation ................................................................................................... 11-2
External Signal Descriptions ......................................................................................... 11-3
Signal Overview ........................................................................................................ 11-3
Detailed Signal Descriptions ..................................................................................... 11-3
Memory Map/Register Definition ................................................................................. 11-4
Register Descriptions................................................................................................. 11-4
I2C Address Register (I2CADR) ........................................................................... 11-5
I2C Frequency Divider Register (I2CFDR)........................................................... 11-5
I2C Control Register (I2CCR) ............................................................................... 11-6
I2C Status Register (I2CSR) .................................................................................. 11-7
I2C Data Register (I2CDR).................................................................................... 11-9
Digital Filter Sampling Rate Register (I2CDFSRR) ........................................... 11-10
Functional Description................................................................................................. 11-10
Transaction Protocol ................................................................................................ 11-10
START Condition .................................................................................................11-11
Slave Address Transmission.................................................................................11-11
Repeated START Condition ................................................................................ 11-12
STOP Condition................................................................................................... 11-12
Protocol Implementation Details ......................................................................... 11-13
Transaction Monitoring—Implementation Details.......................................... 11-13
Control Transfer—Implementation Details ..................................................... 11-13
Address Compare—Implementation Details ....................................................... 11-14
Arbitration Procedure .............................................................................................. 11-14
Arbitration Control .............................................................................................. 11-15
Handshaking ............................................................................................................ 11-15
Clock Control........................................................................................................... 11-15
Clock Synchronization......................................................................................... 11-16
Input Synchronization and Digital Filter ............................................................. 11-16
Input Signal Synchronization .......................................................................... 11-16
Filtering of SCL and SDA Lines ..................................................................... 11-16
Clock Stretching .................................................................................................. 11-17
Boot Sequencer Mode.............................................................................................. 11-17
EEPROM Calling Address .................................................................................. 11-17
EEPROM Data Format ........................................................................................ 11-18
Initialization/Application Information ......................................................................... 11-20
Initialization Sequence............................................................................................. 11-20
Generation of START .............................................................................................. 11-21
MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1
Freescale Semiconductor
xvii
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