MPC9330 查看數據表（PDF） - Motorola => Freescale
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MPC9330 Datasheet PDF : 16 Pages
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MPC9330
Table 7: AC CHARACTERISTICS (VCC = 3.3V ± 5%, TA = –40°C to 85°C)a b
Symbol
Characteristics
Min
Typ
Max
Unit Condition
fref
Input Reference Frequencyc
PLL mode, external feedback
÷ 4 feedbackd
50
÷ 8 feedback
25
÷ 12 feedback 16.67
÷ 16 feedback
12.5
÷ 24 feedback
8.33
PLL mode, internal feedback
〈÷ 16 feedback)
12.5
Input Reference Frequency in PLL bypass modee
100
50
33.3
25
16.67
25
TBD
MHz
MHz
MHz
MHz
MHz
MHz
MHz
PLL locked
fVCO
fXTAL
fMAX
VCO Lock Frequency Rangef
Crystal Interface Frequency Rangeg
Output Frequency
÷ 4 output
÷ 8 output
÷ 12 output
÷ 16 output
÷ 24 output
200
10
50
25
16.67
12.5
8.33
400
20
100
50
33.3
25
16.67
MHz
MHz
MHz
MHz
MHz
MHz
MHz
PLL locked
frefDC
Reference Input Duty Cycle
40
60
%
tr, tf
CCLK Input Rise/Fall Time
t(∅)
Propagation Delay
(static phase offset)
CCLK or PCLK to FB_IN
±100
1.0
ns 0.8 to 2.0V
ps FB_SEL=1 &
PLL locked
tsk(o)
Output-to-Output Skewh
150
ps
DC
Output Duty Cycle
45
50
55
%
tr, tf
Output Rise/Fall Time
0.1
1.0
ns 0.55 to 2.4V
tPLZ, HZ Output Disable Time
10
ns
tPZL, LZ
tJIT(CC)
tJIT(PER)
tJIT(∅)
BW
Output Enable Time
Cycle-to-cycle jitter
Period Jitter
I/O Phase Jitter
PLL closed loop bandwidthj
PLL mode, external feedback
RMS (1s)i
RMS (1s)
RMS (1s)
÷ 4 feedback
÷ 8 feedback
÷ 12 feedback
÷ 16 feedback
÷ 24 feedback
TBD
TBD
TBD
10
ns
ps
ps
ps
TBD
kHz
TBD
kHz
TBD
kHz
TBD
kHz
TBD
kHz
tLOCK Maximum PLL Lock Time
10
ms
a. All AC characteristics are design targets and subject to change upon device characterization.
b. AC characteristics apply for parallel output termination of 50Ω to VTT.
c. PLL mode requires PLL_EN = 0 to enable the PLL.
d. ÷4 feedback (FB) can be accomplished by setting PWR_DN = 0 and the connection of one ÷2 output to FB_IN. See Table 1 to Table 3 for
other feedback configurations.
e. In bypass mode, the MPC9330 divides the input reference clock.
f. The input frequency fref on CCLK must match the VCO frequency range divided by the feedback divider ratio FB: fref = fVCO ÷ FB.
g. The usable crystal frequency range depends on the VCO lock frequency and the PLL feedback ratio.
h. See application section for part–to–part skew calculation.
i. See application section for a jitter calculation for other confidence factors than 1 s.
j. –3 dB point of PLL transfer characteristics.
TIMING SOLUTIONS
5
MOTOROLA
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