MPC9330 查看數據表（PDF） - Motorola => Freescale
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MPC9330 Datasheet PDF : 16 Pages
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MPC9330
Table 8: DC CHARACTERISTICS (VCC = 2.5V ± 5%, TA = –40°C to 85°C)
Symbol
Characteristics
Min
Typ
Max
Unit
Condition
VIH
Input High Voltage
1.7
VCC + 0.3
V
LVCMOS
VIL
VOH
Input Low Voltage
Output High Voltage
–0.3
0.7
V
LVCMOS
1.8
V
IOH=-15 mAa
VOL
ZOUT
Output Low Voltage
Output Impedance
17 - 20
0.6
V
IOL= 15 mA
W
IIN
Input Current
±200
µA VIN = VCC or GND
ICC_PLL Maximum PLL Supply Current
2.0
5.0
mA VCCA Pin
ICC
Maximum Quiescent Supply Current
1.0
mA All VCC Pins
a. The MPC9330 is capable of driving 50Ω transmission lines on the incident edge. Each output drives one 50Ω parallel terminated transmission line
to a termination voltage of VTT. Alternatively, the device drives up to two 50Ω series terminated transmission lines per output.
Table 9: AC CHARACTERISTICS (VCC = 2.5V ± 5%, TA = –40°C to 85°C)a b
Symbol
Characteristics
Min
Typ
Max
Unit Condition
fref
Input Reference Frequencyc
÷ 4 feedbackd
50
PLL mode, external feedback
÷ 8 feedback
25
÷ 12 feedback 16.67
÷ 16 feedback
12.5
÷ 24 feedback
8.33
PLL mode, internal feedback
〈÷ 16 feedback)
12.5
Input Reference Frequency in PLL bypass modee
100
50
33.3
25
16.67
25
TBD
MHz
MHz
MHz
MHz
MHz
MHz
PLL locked
fVCO
fXTAL
fMAX
VCO Lock Frequency Rangef
Crystal Interface Frequency Rangeg
Output Frequency
÷ 4 outputg
÷ 8 output
÷ 12 output
÷ 16 output
÷ 24 output
200
10
50
25
16.67
12.5
8.33
400
20
100
50
33.3
25
16.67
MHz
MHz
MHz
MHz
MHz
MHz
MHz
PLL locked
frefDC
Reference Input Duty Cycle
40
tr, tf
CCLK Input Rise/Fall Time
t(∅)
Propagation Delay
(static phase offset)
CCLK or PCLK to FB_IN
±100
60
%
1.0
ns 0.7 to 1.7V
ps FB_SEL=1 &
PLL locked
tsk(o)
DC
Output-to-Output Skewh
Output Duty Cycle
150
ps
45
50
55
%
tr, tf
tPLZ, HZ
tPZL, LZ
tJIT(CC)
tJIT(PER)
tJIT(∅)
BW
Output Rise/Fall Time
Output Disable Time
Output Enable Time
Cycle-to-cycle jitter
Period Jitter
I/O Phase Jitter
PLL closed loop bandwidthj
0.1
RMS (1s)i
RMS (1s)
RMS (1s)
÷ 4 feedback
÷ 8 feedback
÷ 12 feedback
÷ 16 feedback
÷ 24 feedback
TBD
TBD
TBD
1.0
10
10
TBD
TBD
TBD
TBD
TBD
ns 0.6 to 1.8V
ns
ns
ps
ps
ps
kHz
kHz
kHz
kHz
kHz
tLOCK Maximum PLL Lock Time
10
ms
a. All AC characteristics are design targets and subject to change upon device characterization.
b. AC characteristics apply for parallel output termination of 50Ω to VTT.
c. PLL mode requires PLL_EN = 0 to enable the PLL.
d. ÷4 feedback (FB) can be accomplished by setting PWR_DN = 0 and the connection of one ÷2 output to FB_IN.
See Table 1 to Table 3 for other feedback configurations.
e. In bypass mode, the MPC9330 divides the input reference clock.
f. The input frequency fref on CCLK must match the VCO frequency range divided by the feedback divider ratio FB: fref = fVCO ÷ FB.
g. The usable crystal frequency range depends on the VCO lock frequency and the PLL feedback ratio.
h. See application section for part–to–part skew calculation.
s i. See application section for a jitter calculation for other confidence factors than 1 .
j. –3 dB point of PLL transfer characteristics.
MOTOROLA
6
TIMING SOLUTIONS
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