MPC9448FA 查看數據表（PDF） - Motorola => Freescale

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MPC9448FA

3.3V/2.5V LVCMOS 1:12 Clock Fanout Buffer

Motorola => Freescale 

MPC9448

Freescale Semiconductor, Inc.

PCLK

PCLK

CCLK

VCC

0

CLK

1

STOP

VCC

CLK_SEL

VCC

CLK_STOP

SYNC

VCC

(all input resistors have a value of 25kΩ)

OE

Q0

Q1

Q2

24 23 22 21 20 19 18 17

Q3

Q3

25

16

GND

Q4

VCC

26

Q2

27

Q5

GND

28

Q6

Q1

29

MPC9448

15

Q8

14

VCC

13

Q9

12

GND

Q7

VCC

30

11

Q10

Q0

31

10

VCC

Q8

GND

32

9

Q11

1 234 56 78

Q9

Q10

Q11

Figure 1. Logic Diagram

Figure 2. 32--Lead Package Pinout

(Top View)

Table 1. FUNCTION TABLE

Control

Default

0

CLK_SEL

OE

1

PECL differential input selected

1

Outputs disabled (high-impedance state)1

CLK_STOP

1

Outputs synchronously stopped in logic low state

1. OE=0 will high-impedance tristate all outputs independent on CLK_STOP.

1

CCLK input selected

Outputs enabled

Outputs active

Table 2. PIN CONFIGURATION

Pin

I/O

PCLK, PCLK

Input

CCLK

Input

CLK_SEL

Input

CLK_STOP

Input

OE

Input

Q0--11

Output

GND

Supply

VCC

Supply

Type

LVPECL

LVCMOS

LVCMOS

LVCMOS

LVCMOS

LVCMOS

Ground

VCC

Function

Clock signal input

Alternative clock signal input

Clock input select

Clock output enable/disable

Output enable/disable (high--impedance tristate)

Clock outputs

Negative power supply (GND)

Positive power supply for I/O and core. All VCC pins must be connected to

the positive power supply for correct operation

MOTOROLA

2

For More Information On This Product,

Go to: www.freescale.com

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