MPC953 查看數據表（PDF） - Motorola => Freescale

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MPC953

Low Voltage PLL Clock Driver

Motorola => Freescale 

MPC953

by the impedance mismatch seen looking into the driver. The

parallel combination of the 43Ω series resistor plus the output

impedance does not match the parallel combination of the

line impedances. The voltage wave launched down the two

lines will equal:

VL = VS ( Zo / (Rs + Ro +Zo))

Zo = 50Ω || 50Ω

Rs = 43Ω || 43Ω

Ro = 7Ω

VL = 3.0 (25 / (21.5 + 7 + 25) = 3.0 (25 / 53.5)

= 1.40V

At the load end the voltage will double, due to the near

unity reflection coefficient, to 2.8V. It will then increment

towards the quiescent 3.0V in steps separated by one round

trip delay (in this case 4.0ns).

3.0

OutA

2.5

tD = 3.8956

OutB

tD = 3.9386

2.0

In

1.5

1.0

0.5

0

2

4

6

8

10 12 14

TIME (nS)

Figure 5. Single versus Dual Waveforms

Since this step is well above the threshold region it will not

cause any false clock triggering, however designers may be

uncomfortable with unwanted reflections on the line. To

better match the impedances when driving multiple lines the

situation in Figure 6 should be used. In this case the series

terminating resistors are reduced such that when the parallel

combination is added to the output buffer impedance the line

impedance is perfectly matched.

MPC953

OUTPUT

BUFFER

7Ω

RS = 36Ω ZO = 50Ω

RS = 36Ω ZO = 50Ω

7Ω + 36Ω k 36Ω = 50Ω k 50Ω

25Ω = 25Ω

Figure 6. Optimized Dual Line Termination

SPICE level output buffer models are available for

engineers who want to simulate their specific interconnect

schemes. In addition IV characteristics are in the process of

being generated to support the other board level simulators in

general use.

ECLinPS and ECLinPS Lite

5

DL140 — Rev 3

MOTOROLA

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