MPC9608 查看數據表（PDF） - Motorola => Freescale
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MPC9608 Datasheet PDF : 12 Pages
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Freescale Semiconductor, Inc.
MPC9608
TABLE 7. AC CHARACTERISTICS (VCC = 3.3 V ± 5%, TA = -40° to 85°C)a
Symbol
Characteristics
Min
Typ
fref
Input reference frequency in PLL modeb
F_RANGE = 00
100
F_RANGE = 01
50
F_RANGE = 10
25
F_RANGE = 11
12.5
Input reference frequency in PLL bypass modec
0
fmax
Output Frequencyd
F_RANGE = 00
100
F_RANGE = 01
50
F_RANGE = 10
25
F_RANGE = 11
12.5
tPW, MIN Reference Input Pulse Widthe
2.0
tr, tf
CCLK Input Rise/Fall Time
t(∅)
Propagation Delay (SPO) CCLK to FB_IN
fref = 100 MHz and above
-175
fref = 12.5 MHz to 100 MHz -1.75% of tPER
tSK(o) Output-to-Output Skew
Within a bank
Bank-to-bank
All outputs, inluding QFB
DC
Output Duty Cycle
45
50
tr, tf
tPLZ, HZ
tPZL, LZ
tJIT(CC)
tJIT(PER)
tJIT(∅)
BW
Output Rise/Fall Time
Output Disable Time
Output Enable Time
Cycle-to-cycle jitter
Period Jitter
I/O Phase Jitter
PLL closed loop bandwidthf
0.1
RMS (1 σ)
F_RANGE = 00
F_RANGE = 01
F_RANGE = 10
F_RANGE = 11
7 – 15
2–7
1–3
0.5 – 1.3
tLOCK Maximum PLL Lock Time
10
Max
200
100
50
25
200
200
100
50
25
1.0
+175
+1.75% of tPER
80
100
150
55
1.0
10
10
150
150
125
Unit Condition
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
ns
ns
BSEL = 0
BSEL = 0
BSEL = 0
BSEL = 0
0.8 V to 2.0 V
ps PLL Locked
ps
ps
%
ns
ns
ns
ps
ps
ps
MHz
MHz
MHz
MHz
ms
0.55 V to 2.4 V
BSEL = 0
BSEL = 0
BSEL = 0
a. AC characteristics apply for parallel output termination of 50 Ω to VTT.
b. PLL mode requires PLL_EN = 0 to enable the PLL and zero-delay operation.
c. In bypass mode, the MPC9608 divides the input reference clock.
d. Applies for bank A and for bank B if BSEL = 0. If BSEL = 1, the minimum and maximum output frequency of bank B is divided by two.
e. Calculation of reference duty cycle limits: DCREF, MIN = tPW, MIN * fREF *100% and DCREF, MAX = 100% – DCREF, MIN. For example, at
fREF = 100 MHz the input duty cycle range is 20% < DC < 80%.
f. -3 dB point of PLL transfer characteristics.
TIMING SOLUTIONS
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