MS81V04160-XXTB 查看數據表（PDF） - Oki Electric Industry

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MS81V04160-XXTB

Dual FIFO (262,214-word x 8-Bits) x 2

Oki Electric Industry 

MS81V04160

OKI Semiconductor

Notes: 1. Input signal reference levels for the parameter measurement are VIH = 3.0 V and

VIL = 0 V. The transition time tT is defined to be a transition time that signal transfers

between VIH = 3.0 V and VIL = 0 V.

2. AC measurements assume tT = 3 ns.

3. Read address must have more than a 600 address delay than write address in

every cycle when asynchronous read/write is performed.

4. Read must have more than a 600 address delay than write in order to read the data

written in a current series of write cycles which has been started at last write reset

cycle: this is called "new data read". When read has less than a 70 address delay

than write, the read data are the data written in a previous series of write cycles

which had been written before at last write reset cycle: this is called "old data read".

5. When the read address delay is between more than 71 and less than 599 or more

than 262,214, read data will be undetermined. However, normal write is achieved in

this address condition.

6. Outputs are measured with a load equivalent to 1 TTL load and 30 pF. Output

reference levels are VOH = 1.5 V and VOL = 1.5 V.

7. ( ): MODE2=Vcc

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