MS81V04160 查看數據表（PDF） - Oki Electric Industry

零件编号

产品描述 (功能)

生产厂家

MS81V04160

Dual FIFO (262,214-word x 8-Bits) x 2

Oki Electric Industry 

MS81V04160

OKI Semiconductor

PIN DESCRIPTION

Data Inputs: (DIN 10 - 17)

These pins are used for serial data inputs.

Write Reset: RSTW1

The first positive transition of SWCK after RSTW becomes high resets the write address

pointers to zero. RSTW1 setup and hold times are referenced to the rising edge of SWCK.

Because the write reset function is solely controlled by the SWCK rising edge after the high

level of RSTW, the states of WE1 and IE1 are ignored in the write reset cycle. Before

RSTW1 may be brought high again for a further reset operation, it must be low for at least

two SWCK cycles.

Write Enable: WE1

WE1 is used for data write enable/disable control. WE1 high level enables the input, and

WE1 lowlevel disables the input and holds the internal write address pointer. There are no

WE1 disabletime (low) and WE1 enable time (high) restrictions, because the MS8104160

is in fully static operation as long as the power is on. Note that WE1 setup and hold times

are referenced to the rising edge of SWCK.

Input Enable: IE1

IE1 is used to enable/disable writing into memory. IE1 high level enables writing. The

internal write address pointer is always incremented by cycling SWCK regardless of the

IE1 level. Note that IE1 setup and hold times are referenced to the rising edge of SWCK.

Data Out: (DOUT 0 - 11)

These pins are used for serial data outputs.

Read Reset: RSTR1

The first positive transition of SRCK after RSTR1 becomes high resets the read address

pointers to zero. RSTR1 setup and hold times are referenced to the rising edge of SRCK.

Because the read reset function is solely controlled by the SRCK rising edge after the high

level of RSTR, the states of RE1 and OE1 are ignored in the read reset cycle. Before RSTR

may be brought high again for a further reset operation, it must be low for at least *two

SRCK cycles.

Read Enable: RE1

The function of RE1 is to gate of the SRCK clock for incrementing the read pointer. When

RE1 is high before the rising edge of SRCK, the read pointer is incremented. When RE1 is

low, the read pointer is not incremented. RE1 setup times (tRENS and tRDSS) and RE1

hold times (tRENH and tRDSH) are referenced to the rising edge of the SRCK clock.

Output Enable: OE1

OE1 is used to enable/disable the outputs. OE1 high level enables the outputs. The internal

read address pointer is always incremented by cycling SRCK regardless of the OE1 level.

Note that OE1 setup and hold times are referenced to the rising edge of SRCK.

5

Share Link: