MS81V04160-XXTB 查看數據表（PDF） - Oki Electric Industry

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MS81V04160-XXTB

Dual FIFO (262,214-word x 8-Bits) x 2

Oki Electric Industry 

MS81V04160

OKI Semiconductor

Serial Write Clock: SWCK

The SWCK latches the input data on chip when WE1, 2 is high, and also increments the

internal write address pointer. Data-in setup time tDS, and hold time tDH are referenced to

the rising edge of SWCK.

Serial Read Clock: SRCK

Data is shifted out of the data registers. It is triggered by the rising edge of SRCK when

RE1, 2 is highduring a read operation. The SRCK input increments the internal read

address pointer when RE1,2 is high.

The three-state output buffer provides direct TTL compatibility (no pullup resistor required).

Data out is the same polarity as data in. The output becomes valid after the access time

interval tAC that begins with the rising edge of SRCK. *There are no output valid time

restriction on MS8104160.

Data Input: (DIN 20-27)

These pins are used for serial data inputs.

Write Reset: RSTW2

The first positive transition of SWCK after RSTW becomes high resets the write address

pointers to zero. RSTW2 setup and hold times are referenced to the rising edge of SWCK.

Because the write reset function is solely controlled by the SWCK rising edge after the high

level of RSTW2, the states of WE2 and IE2 are ignored in the write reset cycle. Before

RSTW2 may be brought high again for a further reset operation, it must be low for at least

two SWCK cycles.

Write Enable: WE2

WE is used for data write enable/disable control. WE2 high level enables the input, and

WE2 lowlevel disables the input and holds the internal write address pointer. There are no

WE2 disabletime (low) and WE2 enable time (high) restrictions, because the MS8104160

is in fully static operation as long as the power is on. Note that WE2 setup and hold times

are referenced to the rising edge of SWCK.

Input Enable: IE2

IE2 is used to enable/disable writing into memory. IE2 high level enables writing. The

internal write address pointer is always incremented by cycling SWCK regardless of the

IE2 level. Note that IE2 setup and hold times are referenced to the rising edge of SWCK.

Data Out :
DOUT 20 – 27

These pins are used for serial data outputs.

Read Reset: RSTR2

The first positive transition of SRCK after RSTR2 becomes high resets the read address

pointers to zero. RSTR2 setup and hold times are referenced to the rising edge of SRCK.

Because the read reset function is solely controlled by the SRCK rising edge after the high

level of RSTR2, the states of RE2 and OE2 are ignored in the read reset cycle. Before

RSTR2 may be brought high again for a further reset operation, it must be low for at least

*two SRCK cycles.

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