MS81V04160A 查看數據表（PDF） - Oki Electric Industry

零件编号

产品描述 (功能)

生产厂家

MS81V04160A

Dual FIFO (262,214 Words × 8 Bits) × 2

Oki Electric Industry 

1Semiconductor

FEDS81V04160A-01

MS81V04160A

Power-up and Initialization

On power-up, the device is designed to begin proper operation after at least 100 µs after VCC has stabilized to a

value within the range of recommended operating conditions. After this 100 µs stabilization interval, the following

initialization sequence must be performed.

Because the read and write address pointers are undefined after power-up, a minimum of 80 dummy write

operations (SWCK cycles) and read operations (SRCK cycles) must be performed, followed by an RSTW1, 2

operation and an RSTR1, 2 operation, to properly initialize the write and the read address pointer. Dummy write

cycles/RSTW1, 2 and dummy read cycles/RSTR1, 2 may occur simultaneously.

If these dummy read and write operations start while VCC and/or the substrate voltage has not stabilized, it is

necessary to perform an RSTR1, 2 operation plus a minimum of 80 SRCK cycles plus another RSTR1, 2 operation,

and an RSTW1, 2 operation plus a minimum of 80 SWCK cycles plus another RSTW1, 2 operation to properly

initialize read and write address pointers.

Old/New Data Access

There must be a minimum delay of 150 SWCK cycles between writing into memory and reading out from memory.

If reading from the first field starts with an RSTR1, 2 operation, before the start of writing the second field (before

the next RSTW1, 2 operation), then the data just written will be read out.

The start of reading out the first field of data may be delayed past the beginning of writing in the second field of

data for as many as 20 SWCK cycles. If the RSTR1, 2 operation for the first field read-out occurs less than 20

SWCK cycles after the RSTW1, 2 operation for the second field write-in, then the internal buffering of the device

assures that the first field will still be read out. The first field of data that is read out while the second field of data

is written is called “old data”. In order to read out “new data”, i.e., the second field written in, the delay between an

RSTW1, 2 operation and an RSTR1, 2 operation must be at least 150 SRCK cycles. If the delay between RSTW1,

2 and RSTR1, 2 operations is more than 21 but less than 149 cycles, then the data read out will be undetermined. It

may be “old data” or “new data”, or a combination of old and new data. Such a timing should be avoided.

12/24

Share Link: