MS82V16520A-7GA 查看數據表（PDF） - Oki Electric Industry

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MS82V16520A-7GA

262,144-Word × 32-Bit × 2-Bank SGRAM

Oki Electric Industry 

OKI Semiconductor

FEDS82V16520A-01

MS82V16520A

COMMAND OPERATION

Mode Register Set Command (CS, RAS, CAS, WE = “Low”)

The MS82V16520A has the mode register that defines the operation mode “CAS Latency, Burst Length, Burst

Sequence”. The Mode Register Set command should be executed just after the MS82V16520A is powered on.

Before entering this command, all banks must be precharged. Next command can be issued after tRSC.

Auto Refresh Command (CS, RAS, CAS = “Low”, WE, CKE = “High”)

The Auto Refresh command performs refresh automatically by the address counter. The refresh operation must be

performed 2,048 times within 32 ms and the next command can be issued after tRC from last Auto Refresh

command. Before entering this command, all banks must be precharged.

Self Refresh Entry/Exit Command (CS, RAS, CAS, CKE = “Low”, WE = “High”)

The self refresh operation continues after the Self Refresh Entry command is entered, with CKE level left “low”.

This operation terminates by making CKE level “high”. The self refresh operation is performed automatically by

the internal address counter on the MS82V16520A chip.

In self refresh mode, no external refresh control is required. Before entering self refresh mode, all banks must be

precharged. Next command can be issued after tRC.

Single Bank Precharge Command (CS, RAS, WE, A9 = “Low”, CAS = “High”)

The Single Bank Precharge command triggers bank precharge operation. Precharge bank is selected by BA.

All Bank Precharge Command (CS, RAS, WE = “Low”, CAS, A9 = “High”)

The All Bank Precharge command triggers precharge of both Bank A and Bank B.

Bank Active Command (CS, RAS = “Low”, CAS, WE = ”High”)

The Bank Active command activates the bank selected by BA. The Bank Active command corresponds to

conventional DRAM's RAS falling operation. Row addresses “A0 to A9 and BA” are strobed.

Write Command (CS, CAS, WE, A9 = “Low”, RAS = “High”)

The Write command is required to begin burst write operation. Then burst access initial bit column address is

strobed.

Write with Auto Precharge Command (CS, CAS, WE = “Low”, RAS, A9 = “High”)

The Write with Auto Precharge command is required to begin burst write operation with automatic precharge after

the burst write. Any command that interrupts this operation cannot be issued.

Read Command (CS, CAS, A9 = “Low”, RAS, WE = “High”)

The Read command is required to begin burst read operation. Then burst access initial bit column address is

strobed.

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