¡ Semiconductor
MSC1215-xx
GRID1
GRID2
1 Frame Cycle fFR
4096-bit times
2048-bit times
208-bit times max.
SEG1-17
Figure 6. SEG-GRID output Timing (Dark Mode)
Note: 1. Timing shown for analog dimming with a duty cycle of 208/2048 at VK="H".
2. 1-bit time=TOSC (=4/fOSC)=1.2 µs typical.
90%
VD
(PWM Input)
50%
10%
tr
tf
tPW
T
Figure 7. PWM Waveform
ROW1
ROW2
Keyscan Cycle Time
Keyscan Pulse Width
ROW3
Figure 8. Keyscan Timing
Note: 1. Key scanning from ROW1 to ROW3 is started when any key is pushed down or
released. Scanning will stop when CS turns to "L" from "H", after 2 times of CS pulses
and the transfer of display data.
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