74ACT2708CW 查看數據表（PDF） - Fairchild Semiconductor

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74ACT2708CW

64 x 9 First-In, First-Out Memory

Fairchild Semiconductor 

MODES OF OPERATION

Mode 1: Shift in Sequence for FIFO Empty to Full

Sequence of Operation

1. Input Ready is initially HIGH; HF and FULL flags are

LOW. The FIFO is empty and prepared for valid data.

OR is LOW indicating that the FIFO is not yet ready to

output data.

2. Shift-In is set HIGH, and data is loaded into the FIFO.

Data has to be settled ts before the falling edge of SI

and held th after.

3. Input Ready (IR) goes LOW propagation delay tIR after

SI goes HIGH: input stage is busy.

4. Shift-In is set LOW; IR goes HIGH indicating the FIFO

is ready for additional data. Data just shifted-in arrives

at output propagation delay tOD5 after SI falls. OR goes

HIGH propagation delay tIOR after SI goes LOW, indi-

cating the FIFO has valid data on its outputs. HF goes

HIGH propagation delay tIEafter SI falls, indicating the

FIFO is no longer empty.

5. The process is repeated through the 64th data word.

On the rising edge of the 33rd SI, FULL flag goes HIGH

propagation delay tIHF after SI, indicating a half-full

FIFO. HF goes LOW propagation delay tIF after the ris-

ing edge of the 64th pulse indicating that the FIFO is

full. Any further shift-ins are disabled.

Note: SO and OE are LOW; MR is HIGH.

FIGURE 1. Modes of Operation Mode 1

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