74ACT2708CW 查看數據表（PDF） - Fairchild Semiconductor

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74ACT2708CW

64 x 9 First-In, First-Out Memory

Fairchild Semiconductor 

Mode 2: Master Reset

Sequence of Operation

1. Input and Output Ready, HF and FULL can be in any

state before the reset sequence with Master Reset

(MR) HIGH.

2. Master Reset goes LOW and clears the FIFO, setting

up all essential internal states. Master Reset must be

LOW pulse width tMRW before rising again.

3. Master Reset rises.

4. IR rises (if not HIGH already) to indicate ready to write

state recovery time tMRIRH after the falling edge of MR.

Both HF and FULL will go LOW indicating an empty

FIFO, occurring recovery times tMRE and tMRO respec-

tively after the falling edge of MR. OR falls recovery

time tMRORL after MR falls. Data at outputs goes LOW

recovery time tMRONL after MR goes LOW.

5. Shift-In can be taken HIGH after a minimum recovery

time tMRSIH after MR goes HIGH.

FIGURE 2. Mode of Operation Mode 2

5

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