74ACT2708CW 查看數據表（PDF） - Fairchild Semiconductor

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74ACT2708CW

64 x 9 First-In, First-Out Memory

Fairchild Semiconductor 

Mode 4: Shift-Out Sequence, FIFO Full to Empty

Sequence of Operation

1. FIFO is initially full and OR is HIGH, indicating valid

data is at the output. IR is LOW.

2. SO goes HIGH, resulting in OR going LOW one propa-

gation delay, tOR, after SO rises. OR LOW indicates

output stage is busy.

3. SO goes LOW, new data reaches output one propaga-

tion delay, tD, after SO falls; OR goes HIGH one propa-

gation delay, tOR, after SO falls and HF rises one

propagation delay, tOF, after SO falls. IR rises one fall-

through time, tFT, after SO falls.

4. Repeat process through the 64th SO pulse. FULL flag

goes LOW one propagation delay, tOHF, after the rising

edge of 33rd SO, indicating that the FIFO is less than

half full. On the falling edge of the 64th SO, HF goes

LOW one propagation delay, tOE, after SO, indicating

the FIFO is empty. The SO pulse may rise and fall

again with an attempt to unload an empty FIFO. This

results in no change in the data on the outputs as the

64th word stays latched.

Note: SI and OE are LOW; MR is HIGH; D0–D8 are immaterial.

FIGURE 4. Modes of Operation Mode 4

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