MSM7660 查看數據表（PDF） - Oki Electric Industry
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MSM7660 Datasheet PDF : 35 Pages
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¡ Semiconductor
MSM7660
PIN DESCRIPTIONS
Pin
1
2
3
4
5 to 12
13
14
15 to 22
23
24
25
26
27
28
29
30 to 33
34
35
36
37
38
39
40
41
42
Symbol I/O
Description
X
I Test pin. Normally, to "L" level.
X_L
O Unused pin.
VDD3
Internal logic power supply (3.3 V typ.)
GND
CD[0 to 7] I Chrominance signal input pin (valid only for S video input)
Set to "L" level at composite signal input
VDD5
Peripheral I/O power supply (5 V typ.)
GND
CVBS[0 to 7] I Composite digital data input pin
Luminance signal is input for S video input.
VDD3
Internal logic power supply (3.3 V typ.)
GND
VDD5
Peripheral I/O power supply (5 V typ.)
VDD3
Internal logic power supply (3.3 V typ.)
GND
SCL
I I2C-bus clock pin
SDA
I/O I2C-bus data pin
MODE[0 to 3] I Mode input pins. Dip switches can be used because these pins are
internally pulled-up.
MODE[3] 0: composite
1: S video
MODE[2:0] 000: NTSC ITU-RS601 13.5MHz
001: NTSC Square Pixel 12.27 MHz
010: NTSC 4Fsc
14.32 MHz
100: PAL
ITU-RS601 13.5 MHz
101: PAL
Square Pixel 14.75 MH
others:
Undefined
RESET_L
I System reset input pin (active at "L")
TE
I Test pin. Normally, set to "L" level
TI
I Test pin. Normally, set to "L" level
TO
O Test pin
COEI
I Cascade priority control input pin
Connected to COEO of decoder with higher priority.
COEO
O Cascade priority control output pin
Outputs "L" when COEI is "L" or when this LSI is in output enable status.
OE_L
I Y/C/HSYNC-L/VSYNC-L output enable input pin (active at "L")
OR condition with register setting
GND
VDD3
Internal logic power supply (3.3 V typ.)
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