MSM80C85 查看數據表（PDF） - Oki Electric Industry

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MSM80C85

8-Bit CMOS MICROPROCESSOR

Oki Electric Industry 

¡ Semiconductor

MSM80C85AHRS/GS/JS

MSM80C85AH FUNCTIONAL PIN DEFINITION

The following describes the function of each pin:

Symbol

A8 - A15

(Output, 3-state)

A0 - A7

(Input/Output)

3-state

ALE

(Output)

S0 , S1 , IO/M

(Output)

RD

(Output, 3-state)

WR

(Output, 3-state)

READY

(Input)

HOLD

(Input)

HLDA

(Output)

INTR

(Output)

INTA

(Output)

RST 5.5

RST 6.5

RST 7.5

(Input)

TRAP

(Input)

Function

Address Bus: The most significant 8-bits of the memory address or the 8-bits of the I/O address,

3-stated during Hold and Halt modes and during RESET.

Multiplexed Address/Data Bus: Lower 8-bits of the memory address (or I/O address) appear on

the bus during the first clock cycle (T state) of a machine cycle. It then becomes the data bus during

the second and third clock cycles.

Address Latch Enable: It occurs during the first clock state of a machine cycle and enables address to

get latched into the on-chip latch peripherals. The falling edge of ALE is set to guarantee setup and

hold times for the address information. The falling edge ALE can also be used to strobe the status

information ALE is never 3-state.

Machine cycle status:

IO/M S1 S0

States

IO/M S1 S0

States

0 01

0 10

1 01

1 10

0 11

Memory write

Memory read

I/O write

I/O read

Opcode fetch

1 1 1 Interrupt Acknowledge

. 0 0 Halt = 3-state

. ¥ ¥ Hold

(high impedance)

. ¥ ¥ Reset ¥ = unspecified

S1 can be used as an advanced R/W status. IO/M, S0 and S1 become valid at the beginning of

a machine cycle and remain stable throughout the cycle. The falling edge of ALE may be used to latch

the state of these lines.

READ control: A low level on RD indicates the selected memory or I/O device is to be read that

the Data Bus is available for the data transfer, 3-stated during Hold and Halt modes and during RESET.

WRITE control: A low level on WR indicates the data on the Data Bus is to be written into the selected

memory or I/O location. Data is set up at the trailing edge of WR, 3-stated during Hold and Halt

modes and during RESET.

If READY is high during a read or write cycle, it indicates that the memory or peripheral is ready to

send or receive data. If READY is low, the cpu will wait an integral number of clock cycles for READY

to go high before completing the read or write cycle READY must conform to specified setup and

hold times.

HOLD indicates that another master is requesting the use of the address and data buses.

The cpu, upon receiving the hold request, will relinquish the use of the bus as soon as the completion

of the current bus transfer. Internal processing can continue. The processor can regain the bus only

after the HOLD is removed. When the HOLD is acknowledged, the Address, Data, RD, WR, and IO/M

lines are 3-stated. And status of power down is controlled by HOLD.

HOLD ACKNOWLEDGE: Indicates that the cpu has received the HOLD request and that it will

relinquish the bus in the next clock cycle. HLDA goes low after the Hold request is removed.

The cpu takes the bus one half clock cycle after HLDA goes low.

INTERRUPT REQUEST: Is used as a general purpose interrupt. It is sampled on during the next to

the last clock cycle of an instruction and during Hold and Halt states. If it is active, the Program

Counter (PC) will be inhibited from incrementing and an INTA will be issued. During this cycle

a RESTART or CALL instruction can be inserted to jump to the interrupt service routine.

The INTR is enabled and disabled by software. It is disabled by Reset and immediately after

an interrupt is accepted. Power down mode is reset by INTR.

INTERRUPT ACKNOWLEDGE: Is used instead of (and has the same timing as) RD during

the instruction cycle after an INTR is accepted.

RESTART INTERRUPTS: These three inputs have the same timing as INTR except they cause

an internal RESTART to be automatically inserted.

The priority of these interrupts is ordered as shown in Table 1. These interrupts have a higher priority

than INTR. In addition, they may be individually masked out using the SIM instruction.

Power down mode is reset by these interrupts.

Trap interrupt is a nonmaskable RESTART interrupt. It is recognized at the same timing as INTR or

RST 5.5 - 7.5. It is unaffected by any mask or Interrupt Disable. It has the highest priority of any

interrupt. (See Table 1.) Power down mode is reset by input of TRAP.

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