MSM9000-XX 查看數據表（PDF） - Oki Electric Industry

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产品描述 (功能)

生产厂家

MSM9000-XX

DOT MATRIX LCD CONTROLLER

Oki Electric Industry 

¡ Semiconductor

FEDL9000B-01

MSM9000B-xx

FUNCTIONAL DESCRIPTION

Pin Functional Description

• CS (Chip Select)

Chip select input pin. A logic low on the CS input selects the chip and a logic high on the CS

input does not select the chip. Command and display data inputs can be enabled only when

the chip is selected.

When the input is high, the SO pin and DB0 to DB7 pins are in the high impedance state,

causing SHT, WR and RD pins high level internally.

• WR (Write Enable)

When the parallel interface is used, this pin is the write signal input. Data is written into the

register at the rising edge of WR pulse. When the serial interface is used, this pin is the latch

signal input. This pin is normally high.

• RD (Read Enable)

When the parallel interface is used, this pin is the read signal input. While the pulse is low,

data can be read. The pin is normally high. When this pin is made low with C/D set low, the

display data pointed to by the address pointer is output from DB0 to DB7. When the pin is

made low with C/D set high, busy data is output from DB0 and low signals are output from

DB1 to DB7. After the rising edge of WR, busy data (H) is output. The data automatically

changes to non-busy (L) after the specified time elapses.

When the serial interface is used, fix this pin to "H" or "L".

• C/D (Command/Data Select)

This input pin selects whether the data to be input to the SI pin and the DB7 to DB0 pins is

handled as a command or display data, depending on the state of the pin at the rising edge

of WR. When the pin is H, the input data is handled as a command. When the pin is L, display

data is input.

• DB0 to DB7 (Data Buses 0 to 7)

Data input and output pins for the parallel interface. Normally data buses 0 to 7 are in high

impedance, when RD is driven low, display data and the busy signal are output.

When the serial interface is used, leave this pin open.

• SI (Serial Data Input)

Data input pin for the serial interface. Commands and display data are read at the rising edge

of SHT and written to registers at the rising edge of WR. The eight-bit data immediately before

the rising edge of WR is valid.

When the parallel interface is used, fix this pin to "H" or "L".

• SO (Serial Data Output)

Data output pin for the serial interface. The display data pointed to by the address pointer is

output at the rising edge of SHT. After the rising edge of WR, busy data (H) is output.

The data automatically changes to non-busy (L) after the specified time elapses.

When the parallel interface is used, this pin remains in the high impedance state.

• SHT (Shift Clock)

Clock input pin to input and output serial interface data. Data input is synchronous with the

rising edge of the clock, and the data output is synchronous with the falling edge of the clock.

This pin is normally high.

When the parallel interface is used, fix this pin to "H" or "L".

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