MSM9225B 查看數據表（PDF） - Oki Electric Industry

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MSM9225B

CAN (Controller Area Network) Controller

Oki Electric Industry 

1Semiconductor

FEDL9225B-03

MSM9225B

PIN DESCRIPTIONS

Symbol

CS

A7-0

AD7-0/

D7-0

PWR

PRD/

SRW

PALE

SDI

SDO

SCLK

PRDY/

SWAIT

Pin

10

41-44, 1-4

31-38

26

9

27

7

5

8

16

Type

Description

Chip select pin. When “L”, PALE, PWR, PRD/SRW, SCLK and SDO

I pins (microcontroller interface pins) are valid.

When “H”, these pins are invalid.

Address bus pins (when using separate buses). If used with a

I multiplexed bus or if used in the serial mode, fix these pins at “H” or “L”

levels.

Multiplexed bus: Address/data pins (AD7-0)

I/O Separate buses: Data pins (D7-0)

If used in the serial mode, fix these pins at a “L” levels.

Write input pin if used in the parallel mode. Data is captured when this

I pin is at a “L” level.

If used in the serial mode, fix this pin at a “L” level.

Parallel mode: Read signal pin (PRD)

When at a “L” level, data is output from the data pins.

I

Serial mode: Read/write signal pin (SRW)

When at a “H” level, data is output from the SDO pin.

When at a “L” level, the SDO pin is at high impedance, and data is

captured beginning with the second byte of data input from the SDI pin.

Address latch signal pin

When at a “H” level, addresses are captured.

I If used in the parallel mode and the address latch signal is unnecessary

or in the serial mode, fix this pin at a “H” or “L” level.

Serial data input pin

I

Addresses (1st byte) and data (beginning from the 2nd byte) are input to

this pin, LSB first. If used in the parallel mode, fix this pin at a “H” or “L”

level.

Serial data output pin

O

When the CS pin is at a “H” level, this pin is at high impedance. When

CS is at a “L” level, data is output from this pin, LSB first.

If used in the parallel mode, fix this pin at a “H” or “L” level.

Shift clock input pin for serial data

I At the rising edge of the shift clock, SDI pin data is captured. At the

falling edge, data is output from the SDO pin.

Ready output pin

When required by the MSM9225B, a signal may be output to extend the

bus cycle until the internal access is completed.

Internal access in

O

Parallel mode

(PRDY)

progress

“L” level output

Serial mode

(SWAIT)

“H” level output

After completion of

access

High impedance

output

“L” level output

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