MT28F322P3 查看數據表（PDF） - Micron Technology

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MT28F322P3

FLASH MEMORY

Micron Technology 

PRELIMINARY

2 MEG x 16

ASYNC/PAGE FLASH MEMORY

Table 5

Command Descriptions

CODE DEVICE MODE BUS CYCLE

DESCRIPTION

10h Alt. Program Setup First

Operates the same as a PROGRAM SETUP command.

20h Erase Setup

First

Prepares the CSM for an ERASE CONFIRM command. If the next

command is not an ERASE CONFIRM command, the command will

be ignored, and the bank will go to the read array mode and wait

for another command.

30h FPA Setup

First

Prepares the CSM for an FPA CONFIRM command.

40h Program Setup

First

A two-cycle command: The first cycle prepares for a PROGRAM

operation, and the second cycle latches addresses and data and

initiates the WSM to execute the program algorithm. The Flash

device outputs status register data on the falling edge of OE# or CE#,

whichever occurs first.

50h Clear Status

Register

First

The WSM can set the block lock status (SR3), program status (SR4),

and erase status (SR5) bits in the status register to “1,” but it cannot

clear them to “0.” Issuing this command clears those bits to “0.”

60h Protection

Configuration

Setup

First

Prepares the CSM for changes to the block locking status. If the next

command is not BLOCK UNLOCK, BLOCK LOCK or BLOCK LOCK

DOWN, the command will be ignored, and the device will go to read

status mode.

70h Read Status

Register

First

Places the device into read status register mode. Reading the device

will output the contents of the status register for the addressed bank.

The device will automatically enter this mode for the addressed bank

after a PROGRAM or ERASE operation has been initiated.

90h Read Protection

Configuration

First

Puts the device into the read protection configuration mode so that

reading the device will output the manufacturer/device codes or

block lock status.

98h Read Query

First

Puts the device into the read query mode so that reading the device

will output common Flash interface information.

B0h Program/Erase

Suspend

First

Suspends the currently executing PROGRAM/ERASE operation. The

status register will indicate when the operation has been successfully

suspended by setting either the program suspend (SR2) or erase

suspend (SR6), and the WSM status bit (SR7) to a “1” (ready). The

WSM will continue to idle in the suspend state, regardless of the state

of all input control signals except RST#, which will immediately shut

down the WSM and the remainder of the chip if RST# is driven to VIL.

C0h Program Device

First

Protection Register

Writes a specific code into the device protection register.

Lock Device

Protection Register

First

Locks the device protection register; data can no longer be changed.

(continued on the next page)

2 Meg x 16 Async/Page Flash Memory

MT28F322P3FJ_3.p65 – Rev. 3, Pub. 7/02

10

Micron Technology, Inc., reserves the right to change products or specifications without notice.

©2002, Micron Technology, Inc.

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