MT28F322P3 查看數據表（PDF） - Micron Technology

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MT28F322P3

FLASH MEMORY

Micron Technology 

PRELIMINARY

2 MEG x 16

ASYNC/PAGE FLASH MEMORY

COMMAND STATE MACHINE (CSM)

Commands are issued to the command state ma-

chine (CSM) using standard microprocessor write tim-

ings. The CSM acts as an interface between external

microprocessors and the internal WSM. The available

commands are listed in Table 3, their definitions are

given in Table 4, and their descriptions in Table 5.

Program and erase algorithms are automated by an

on-chip WSM. For more specific information about the

CSM transition states, see Micron technical note

TN-28-33, “Command State Machine Description and

Command Definition.”

Once a valid PROGRAM/ERASE command is en-

tered, the WSM executes the appropriate algorithm,

which generates the necessary timing signals to con-

trol the device internally and accomplish the requested

operation. A command is valid only if the exact se-

quence of WRITEs is completed. After the WSM com-

pletes its task, the WSM status bit (SR7) (see Table 7) is

set to a logic HIGH level (1), allowing the CSM to re-

spond to the full command set again.

OPERATIONS

Device operations are selected by entering a stan-

dard JEDEC 8-bit command code with conventional

microprocessor timings into an on-chip CSM through

I/Os DQ0–DQ7. The number of bus cycles required to

activate a command is typically one or two. The first

operation is always a WRITE. Control signals CE# and

WE# must be at a logic LOW level (VIL), and OE# and

RST# must be at logic HIGH (VIH). The second opera-

tion, when needed, can be a WRITE or a READ depend-

ing upon the command. During a READ operation, con-

trol signals CE# and OE# must be at a logic LOW level

(VIL), and WE# and RST# must be at logic HIGH (VIH).

Table 6 shows the bus operations for all the modes:

write, read, reset, standby, and output disable.

When the device is powered up, internal reset cir-

cuitry initializes the chip to a read array mode of opera-

tion. Changing the mode of operation requires that a

command code be entered into the CSM. For each one

of the two memory partitions, an on-chip status regis-

ter is available. These two registers allow the progress

of the various operations that can take place on a

memory bank to be monitored. One of the two status

registers is interrogated by entering a READ STATUS

REGISTER command onto the CSM (cycle 1), specify-

ing an address within the memory partition boundary,

and reading the register data on I/Os DQ0–DQ7

(cycle 2). Status register bits SR0-SR7 correspond to

DQ0–DQ7 (see Table 7).

COMMAND DEFINITION

Once a specific command code has been entered,

the WSM executes an internal algorithm, generating

the necessary timing signals to program, erase, and

verify data. See Table 4 for the CSM command defini-

tions and data for each of the bus cycles.

STATUS REGISTER

The status register allows the user to determine

whether the state of a PROGRAM/ERASE operation is

pending or complete. The status register is monitored

by toggling OE# and CE# and reading the resulting

status code on I/Os DQ0–DQ7. The high-order I/Os

Table 3

Command State Machine Codes For Device Mode Selection

COMMAND DQ0–DQ7

40h/10h

20h

30h

50h

60h

70h

90h

98h

B0h

C0h

D0h

FFh

CODE ON DEVICE MODE

Program setup/alternate program setup

Block erase setup

Fast programming algorithm setup

Clear status register

Protection configuration setup

Read status register

Read protection configuration register

Read query

Program/erase suspend

Protection register program/lock

Program/erase resume – erase confirm

Read array

2 Meg x 16 Async/Page Flash Memory

MT28F322P3FJ_3.p65 – Rev. 3, Pub. 7/02

8

Micron Technology, Inc., reserves the right to change products or specifications without notice.

©2002, Micron Technology, Inc.

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