MT28F322P3 查看數據表（PDF） - Micron Technology
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MT28F322P3 Datasheet PDF : 36 Pages
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(DQ8–DQ15) are set to 00h internally, so only the low-
order I/Os (DQ0–DQ7) need to be interpreted. Address
lines select the status register pertinent to the selected
memory partition.
Register data is updated and latched on the falling
edge of OE# or CE#, whichever occurs last. Latching the
data prevents errors from occurring if the register input
changes during a status register read.
The status register provides the internal state of the
WSM to the external microprocessor. During periods
when the WSM is active, the status register can be polled
to determine the WSM status. Table 7 defines the sta-
tus register bits.
After monitoring the status register during a
PROGRAM/ERASE operation, the data appearing on
DQ0–DQ7 remains as status register data until a new
command is issued to the CSM. To return the device to
other modes of operation, a new command must be
issued to the CSM.
PRELIMINARY
2 MEG x 16
ASYNC/PAGE FLASH MEMORY
CSM OPERATIONS
The CSM decodes instructions for read array, read
protection configuration register, read query, read sta-
tus register, clear status register, program, erase, erase
suspend, erase resume, program suspend, program
resume, lock block, unlock block, and lock down block,
chip protection program, and set read configuration
register. The 8-bit command code is input to the device
on DQ0–DQ7 (see Table 3 for CSM codes and Table 4
for command definitions). During a PROGRAM or
ERASE cycle, the CSM informs the WSM that a PRO-
GRAM or ERASE cycle has been requested.
During a PROGRAM cycle, the WSM controls the
program sequences and the CSM responds to a PRO-
GRAM SUSPEND command only.
During an ERASE cycle, the CSM responds to an
ERASE SUSPEND command only. When the WSM has
completed its task, the WSM status bit (SR7) is set to a
Table 4
Command Definitions
FIRST BUS CYCLE
SECOND BUS CYCLE
COMMAND
OPERATION ADDRESS1 DATA OPERATION ADDRESS1 DATA1
READ ARRAY
WRITE
WA
FFh
READ PROTECTION CONFIGURATION REGISTER WRITE
IA
90h
READ
IA
ID
READ STATUS REGISTER
WRITE
BA
70h
READ
X
SRD
CLEAR STATUS REGISTER
WRITE
BA
50h
READ QUERY
WRITE
QA
98h
READ
QA
QD
BLOCK ERASE SETUP
WRITE
BA
20h
WRITE
BA
D0h
PROGRAM SETUP/ALTERNATE PROGRAM SETUP WRITE
WA 40h/10h WRITE
WA
WD
FAST PROGRAMMING ALGORITHM SETUP
WRITE
WA
30h
WRITE
WA
D0h
PROGRAM/ERASE SUSPEND
WRITE
BA
B0h
PROGRAM/ERASE RESUME - ERASE CONFIRM
WRITE
BA
D0h
LOCK BLOCK
WRITE
BA
60h
WRITE
BA
01h
UNLOCK BLOCK
WRITE
BA
60h
WRITE
BA
D0h
LOCK DOWN BLOCK
WRITE
BA
60h
WRITE
BA
2Fh
PROTECTION REGISTER PROGRAM
WRITE
PA
C0h
WRITE
PA
PD
PROTECTION REGISTER LOCK
WRITE
LPA
C0h
WRITE
LPA
FFFDh
NOTE:
1. BA: Address within the block
IA: Identification code address
ID: Identification code data
LPA: Lock protection register address
PA: Protection register address
PD: Data to be written at location PA
QA: Query code address
QD: Query code data
SRD: Data read from the status register
WA: Word address of memory location to be
written, or read
WD: Data to be written at the location WA
X: “Don’t Care”
2 Meg x 16 Async/Page Flash Memory
MT28F322P3FJ_3.p65 – Rev. 3, Pub. 7/02
9
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
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