MT16VDDF12864HY-262 查看數據表（PDF） - Micron Technology

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MT16VDDF12864HY-262

SMALL-OUTLINE DDR SDRAM DIMM

Micron Technology 

Notes

1. All voltages referenced to VSS.

2. Tests for AC timing, IDD, and electrical AC and DC

characteristics may be conducted at nominal ref-

erence/supply voltage levels, but the related spec-

ifications and device operation are guaranteed for

the full voltage range specified.

3. Outputs measured with equivalent load:

VTT

Output

(VOUT)

50Ω

Reference

Point

30pF

4. AC timing and IDD tests may use a VIL-to-VIH

swing of up to 1.5V in the test environment, but

input timing is still referenced to VREF (or to the

crossing point for CK/CK#), and parameter speci-

fications are guaranteed for the specified AC input

levels under normal use conditions. The mini-

mum slew rate for the input signals used to test

the device is 1V/ns in the range between VIL(AC)

and VIH(AC).

5. The AC and DC input level specifications are as

defined in the SSTL_2 Standard (i.e., the receiver

will effectively switch as a result of the signal

crossing the AC input level, and will remain in that

state as long as the signal does not ring back

above [below] the DC input LOW [HIGH] level).

6. VREF is expected to equal VDDQ/2 of the transmit-

ting device and to track variations in the DC level

of the same. Peak-to-peak noise (non-common

mode) on VREF may not exceed ±2 percent of the

DC value. Thus, from VDDQ/2, VREF is allowed

±25mV for DC error and an additional ±25mV for

AC noise. This measurement is to be taken at the

nearest VREF bypass capacitor.

7. VTT is not applied directly to the device. VTT is a

system supply for signal termination resistors, is

expected to be set equal to VREF and must track

variations in the DC level of VREF.

8. IDD is dependent on output loading and cycle

rates. Specified values are obtained with mini-

mum cycle time at CL = 2 for -262, -26A, and -202,

CL = 2.5 for-335 and -265 with the outputs open.

9. Enables on-chip refresh and address counters.

10. IDD specifications are tested after the device is

properly initialized, and is averaged at the defined

cycle rate.

11. This parameter is sampled. VDD = +2.5V ±0.2V,

VDDQ = +2.5V ±0.2V, VREF = VSS, f = 100 MHz, =

512MB, 1GB (x64)

200-PIN DDR SODIMM

25°C, VOUT(DC) = VDDQ/2, VOUT (peak to peak) TA

= 0.2V. DM input is grouped with I/O pins, reflect-

ing the fact that they are matched in loading.

12. Command/Address input slew rate = 0.5V/ns. For

-262, -26A, and -265 with slew rates 1V/ns and

faster, tIS and tIH are reduced to 900ps; for -335,

they are reduced to 750ps. If the slew rate is less

than 0.5 V/ns, timing must be derated: tIS has an

additional 50ps per each 100mV/ns reduction in

slew rate from the 500mV/ns, while tIH remains

constant. If the slew rate exceeds 4.5V/ns, func-

tionality is uncertain.

13. The CK/CK# input reference level (for timing ref-

erenced to CK/CK#) is the point at which CK and

CK# cross; the input reference level for signals

other than CK/CK# is VREF.

14. Inputs are not recognized as valid until VREF stabi-

lizes. Exception: during the period before VREF

stabilizes, CKE £ 0.3 x VDDQ is recognized as LOW.

15. The output timing reference level, as measured at

the timing reference point indicated in Note 3, is

VTT.

16. tHZ and tLZ transitions occur in the same access

time windows as valid data transitions. These

parameters are not referenced to a specific voltage

level, but specify when the device output is no

longer driving (HZ) or begins driving (LZ).

17. The intent of the Don’t Care state after completion

of the postamble is the DQS-driven signal should

either be high, low, or high-Z and that any signal

transition within the input switching region must

follow valid input requirements. That is, if DQS

transitions high (above VIH DC (MIN) then it must

not transition low (below VIH DC) prior to tDQSH

(MIN).

18. This is not a device limit. The device will operate

with a negative value, but system performance

could be degraded due to bus turnaround.

19. It is recommended that DQS be valid (HIGH or

LOW) on or before the WRITE command. The

case shown (DQS going from High-Z to logic

LOW) applies when no WRITEs were previously in

progress on the bus. If a previous WRITE was in

progress, DQS could be HIGH during this time,

depending on tDQSS.

20. MIN (tRC or tRFC) for IDD measurements is the

smallest multiple of tCK that meets the minimum

absolute Value for the respective parameter. tRAS

(MAX) for IDD measurements is the largest multi-

09005aef80a646bc

DDF16C64_128x64HG_B.fm - Rev. B 7/03 EN

20

Micron Technology, Inc., reserves the right to change products or specifications without notice.

©2003 Micron Technology, Inc.

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