MT16VDDF12864HG-26A 查看數據表（PDF） - Micron Technology
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MT16VDDF12864HG-26A Datasheet PDF : 31 Pages
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Burst Length
Read and write accesses to the DDR SDRAM are
burst oriented, with the burst length being program-
mable, as shown in Figure 5, Mode Register Definition
Diagram. The burst length determines the maximum
number of column locations that can be accessed for a
given READ or WRITE command. Burst lengths of 2, 4,
or 8 locations are available for both the sequential and
the interleaved burst types.
Reserved states should not be used, as unknown
operation or incompatibility with future versions may
result.
When a READ or WRITE command is issued, a block
of columns equal to the burst length is effectively
selected. All accesses for that burst take place within
this block, meaning that the burst will wrap within the
block if a boundary is reached. The block is uniquely
selected by A1–Ai when the burst length is set to two,
by A2–Ai when the burst length is set to four and by
A3–Ai when the burst length is set to eight (where Ai is
the most significant column address bit for a given
configuration. See Note 5 of Table 6, Burst Definition
Table, on page 10, for Ai values). The remaining (least
significant) address bit(s) is (are) used to select the
starting location within the block. The programmed
burst length applies to both read and write bursts.
Burst Type
Accesses within a given burst may be programmed
to be either sequential or interleaved; this is referred to
as the burst type and is selected via bit M3.
The ordering of accesses within a burst is deter-
mined by the burst length, the burst type and the start-
ing column address, as shown in Table 6, Burst
Definition Table, on page 10.
Read Latency
The READ latency is the delay, in clock cycles,
between the registration of a READ command and the
availability of the first bit of output data. The latency
can be set to 2 or 2.5 clocks, as shown in Figure 6, CAS
Latency Diagram, on page 10.
If a READ command is registered at clock edge n,
and the latency is m clocks, the data will be available
nominally coincident with clock edge n + m. The CAS
Latency Table indicates the operating frequencies at
which each CAS latency setting can be used.
512MB, 1GB (x64)
200-PIN DDR SODIMM
Reserved states should not be used as unknown
operation or incompatibility with future versions may
result.
Figure 5: Mode Register Definition
Diagram
BA1 BA0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus
14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Mode Register (Mx)
0* 0* Operating Mode CAS Latency BT Burst Length
* M14 and M13 (BA1 and BA0)
must be “0, 0” to select the
base mode register (vs. the
extended mode register).
Burst Length
M2 M1 M0
0 00
0 01
0 10
0 11
1 00
1 01
1 10
1 11
M3 = 0
Reserved
2
4
8
Reserved
Reserved
Reserved
Reserved
M3
Burst Type
0
Sequential
1
Interleaved
M6 M5 M4
000
001
010
011
100
101
110
111
CAS Latency
Reserved
Reserved
2
Reserved
Reserved
Reserved
2.5
Reserved
M13 M12 M11 M10 M9 M8 M7
0 0 0 0 0 00
0 0 0 0 0 10
- - - - - --
M6-M0
Valid
Valid
-
Operating Mode
Normal Operation
Normal Operation/Reset DLL
All other states reserved
09005aef80a646bc
DDF16C64_128x64HG_B.fm - Rev. B 7/03 EN
9
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc.
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