128M16 查看數據表（PDF） - Micron Technology

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128M16

DDR3 SDRAM

Micron Technology 

2Gb: x4, x8, x16 DDR3 SDRAM

Functional Description

• Complete functionality may be described throughout the document; any page or dia-

gram may have been simplified to convey a topic and may not be inclusive of all re-

quirements.

• Any specific requirement takes precedence over a general statement.

• Any functionality not specifically stated is considered undefined, illegal, and not sup-

ported, and can result in unknown operation.

• Row addressing is denoted as A[n:0]. For example, 1Gb: n = 12 (x16); 1Gb: n = 13 (x4,

x8); 2Gb: n = 13 (x16) and 2Gb: n = 14 (x4, x8); 4Gb: n = 14 (x16); and 4Gb: n = 15 (x4,

x8).

• Dynamic ODT has a special use case: when DDR3 devices are architected for use in a

single rank memory array, the ODT ball can be wired HIGH rather than routed. Refer

to the Dynamic ODT Special Use Case section.

• A x16 device's DQ bus is comprised of two bytes. If only one of the bytes needs to be

used, use the lower byte for data transfers and terminate the upper byte as noted:

– Connect UDQS to ground via 1kΩ* resistor.

– Connect UDQS# to VDD via 1kΩ* resistor.

– Connect UDM to VDD via 1kΩ* resistor.

– Connect DQ[15:8] individually to either VSS, VDD, or VREF via 1kΩ resistors,* or float

DQ[15:8].

*If ODT is used, 1kΩ resistor should be changed to 4x that of the selected ODT.

PDF: 09005aef826aaadc

2Gb_DDR3_SDRAM.pdf - Rev. Q 04/13 EN

13

Micron Technology, Inc. reserves the right to change products or specifications without notice.

‹ 2006 Micron Technology, Inc. All rights reserved.

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