128M16 查看數據表（PDF） - Micron Technology

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128M16

DDR3 SDRAM

Micron Technology 

2Gb: x4, x8, x16 DDR3 SDRAM

Ball Assignments and Descriptions

Table 3: 78-Ball FBGA – x4, x8 Ball Descriptions (Continued)

Symbol

DQ[3:0]

DQ[7:0]

DQS, DQS#

TDQS, TDQS#

VDD

VDDQ

VREFCA

VREFDQ

VSS

VSSQ

ZQ

NC

NF

Type

I/O

I/O

I/O

Output

Supply

Supply

Supply

Supply

Supply

Supply

Reference

–

–

Description

Data input/output: Bidirectional data bus for the x4 configuration. DQ[3:0] are

referenced to VREFDQ.

Data input/output: Bidirectional data bus for the x8 configuration. DQ[7:0] are

referenced to VREFDQ.

Data strobe: Output with read data. Edge-aligned with read data. Input with write

data. Center-aligned to write data.

Termination data strobe: Applies to the x8 configuration only. When TDQS is

enabled, DM is disabled, and the TDQS and TDQS# balls provide termination

resistance.

Power supply: 1.5V ±0.075V.

DQ power supply: 1.5V ±0.075V. Isolated on the device for improved noise immuni-

ty.

Reference voltage for control, command, and address: VREFCA must be

maintained at all times (including self refresh) for proper device operation.

Reference voltage for data: VREFDQ must be maintained at all times (excluding self

refresh) for proper device operation.

Ground.

DQ ground: Isolated on the device for improved noise immunity.

External reference ball for output drive calibration: This ball is tied to external

240Ω resistor RZQ, which is tied to VSSQ.

No connect: These balls should be left unconnected (the ball has no connection to

the DRAM or to other balls).

No function: When configured as a x4 device, these balls are NF. When configured

as a x8 device, these balls are defined as TDQS#, DQ[7:4].

PDF: 09005aef826aaadc

2Gb_DDR3_SDRAM.pdf - Rev. Q 04/13 EN

19

Micron Technology, Inc. reserves the right to change products or specifications without notice.

‹ 2006 Micron Technology, Inc. All rights reserved.

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