MT88E39 查看數據表（PDF） - Zarlink Semiconductor Inc
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MT88E39 Datasheet PDF : 16 Pages
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MT88E39
Data Sheet
Message Waiting Indicator) applications. When the batteries are drained, the CPE will not meet the reject level. For
on-hook Caller ID, there is no reject level and the CPE will meet all requirements.
Input Configuration
The input arrangement of the MT88E39 provides an operational amplifier, as well as a bias source (VRef) which is
used to bias the inputs at VDD/2. Provision is made for connection of a feedback resistor to the op-amp output (GS)
for adjustment of gain.
Figure 3 shows the necessary connections for a differential input configuration. In a single-ended configuration, the
input pins are connected as shown in Figure 4.
C1 R1
IN+
IN-
C2 R4
R5
GS
R3
R2
VRef
DIFFERENTIAL INPUT AMPLIFIER
C1 = C2
MT88E39
R1 = R4
R3 = (R2 x R5) / (R2 + R5)
For unity gain, R5 = R1
VOLTAGE GAIN
INPUT IMPEDANCE
(AVdiff) = R5/R1
(ZINdiff) = 2 R12 + (1/ωC)2
Figure 3 - Differential Input Configuration
IN+
IN-
C
RIN
RF
GS
VOLTAGE GAIN
(AV) = RF / RIN
VRef
MT88E39
Figure 4 - Single-Ended Input Configuration
3-wire FSK Data Interface
The MT88E39 provides a powerful dual mode 3-wire interface so that the 8-bit data words in the demodulated FSK
bit stream can be extracted without the need either for an external UART or for the microcontroller to perform the
UART function in software. The interface is specifically designed for the 1200 baud rate and is comprised of the
DATA, DCLK (data clock) and DR (data ready) pins. Two modes (0 and 1) are selectable via control of the device’s
MODE pin. In mode 0 the FSK bit stream is output as demodulated. In mode 1 the FSK data byte is store in a 1 byte
buffer. Note that in mode 0 DR and CD are open drain outputs; in mode 1 they are CMOS outputs. DCLK is an
output in mode 0, an input in mode 1.
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