MT9072AB 查看數據表（PDF） - Zarlink Semiconductor Inc

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MT9072AB

Octal T1/E1/J1 Framer

Zarlink Semiconductor Inc 

MT9072

Data Sheet

MT9072 Detailed Feature Summary

Standards Compliance and Support

T1/J1 Mode

ANSI:

T1.102, T1.231

T1.403, T1.408

AT&T:

TR 62411, PUB43801

Telcordia:

GR-303-CORE

ITU-T:

G.802

TTC:

JT-G703, JT-G704

JT-G706

ETSI:

E1 Mode

TBR4, TBR13

ETS 300 233, ETS 300 347 (V5.2)

ITU-T:

G.703, G.704, G.706, G.711, G.732

G.775, G.796, G.823, I.431

G.965 (V5.2)

Access and Control

• A 16-bit parallel Motorola or Intel non-multiplexed microprocessor interface is used to access the control and

status registers

Backplane Interfaces

• 2.048 Mbit/s or 8.192 Mbit/s ST-BUS

• 2.048 Mbit/s GCI bus

• IMA (Inverse Mux for ATM) mode, 1.544 Mbit/s (T1) or 2.048 Mbit/s (E1) serial bus with asynchronous

transmit and receive timing for Inverse MUX for ATM applications.

• CSTo/CSTi pins can be used to access the receive/transmit signaling data

• RxDL pin can be used to access the entire B8ZS/HDB3 decoded receive stream including framing bits

• TxDL pin can be used to transmit data on the FDL (T1) or the Sa bits (E1)

T1/J1 Mode

• PCM24 channels 1-24 are mapped to ST-BUS

channels 0-23 respectively

• The framing-bit is mapped to ST-BUS channel

31

E1 Mode

• PCM30 timeslots 0-31 are mapped to ST-BUS

channels 0-31 respectively

2

Zarlink Semiconductor Inc.

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