CY7C10211B-10VC 查看數據表（PDF） - Cypress Semiconductor
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CY7C10211B-10VC Datasheet PDF : 10 Pages
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CY7C1021B
CY7C10211B
Capacitance[5]
Parameter
CIN
COUT
Description
Input Capacitance
Output Capacitance
Test Conditions
TA = 25°C, f = 1 MHz,
VCC = 5.0V
Max.
Unit
8
pF
8
pF
AC Test Loads and Waveforms
R 481 Ω
5V
R 481 Ω
5V
3.0V
OUTPUT
OUTPUT
30 pF
INCLUDING
JIG AND
SCOPE
(a)
R2
255 Ω
5 pF
INCLUDING
JIG AND
SCOPE
(b)
Equivalent to: THÉVENIN OUTPUT
EQUIVALENT
167
30 pF
R2 GND
255 Ω
Rise Time: 1 V/ns
1.73V
ALL INPUT PULSES
90%
90%
10%
10%
Fall Time:1 V/ns
Switching Characteristics[6] Over the Operating Range
7C10211B-10
7C1021B-12
7C1021B-15
Parameter
Description
Min. Max. Min. Max. Min. Max. Unit
Read Cycle
tRC
tAA
tOHA
tACE
tDOE
tLZOE
tHZOE
tLZCE
tHZCE
tPU
tPD
tDBE
tLZBE
tHZBE
Write Cycle[9]
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low Z[7]
OE HIGH to High Z[7, 8]
CE LOW to Low Z[7]
CE HIGH to High Z[7, 8]
CE LOW to Power-Up
CE HIGH to Power-Down
Byte Enable to Data Valid
Byte Enable to Low Z
Byte Disable to High Z
10
12
15
ns
10
12
15
ns
3
3
3
ns
10
12
15
ns
5
6
7
ns
0
0
0
ns
5
6
7
ns
3
3
3
ns
5
6
7
ns
0
0
0
ns
10
12
15
ns
5
6
7
ns
0
0
0
ns
5
6
7
ns
tWC
Write Cycle Time
10
12
15
ns
tSCE
CE LOW to Write End
8
9
10
ns
tAW
Address Set-Up to Write End
7
8
10
ns
tHA
Address Hold from Write End
0
0
0
ns
tSA
Address Set-Up to Write Start
0
0
0
ns
tSD
Data Set-Up to Write End
5
6
8
ns
tHD
Data Hold from Write End
0
0
0
ns
Notes:
6. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
IOL/IOH and 30-pF load capacitance.
7. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
8. tHZOE, tHZBE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage.
9. The internal write time of the memory is defined by the overlap of CE LOW, WE LOW and BHE / BLE LOW. CE, WE and BHE / BLE must be LOW to initiate a write,
and the transition of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write.
Document #: 38-05145 Rev. *A
Page 4 of 10
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