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MT90866AG2 查看數據表(PDF) - Zarlink Semiconductor Inc

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MT90866AG2 Datasheet PDF : 86 Pages
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MT90866
Data Sheet
The MT90866 also offers a sub-rate switching configuration which allows 2-bit wide 16kb/s or 4-bit wide 32 kb/s
data channels to be switched within the device.
The device has features that are programmable on a per-stream or a per-channel basis including message mode,
input delay offset, output advancement offset, direction control, and high impedance output control.
The MT90866 supports all three of the H.110 specification required clocking modes: Primary Master, Secondary
Master and Slave.
VDD5V VDD VSS
PCI_OE ODE
STio0
STio31
BCSTo
C20i
TM1
TM2
SG1
AT1
DT1
RESET
Backplane
Interface
S/P
&
P/S
Converter
HiZ
Control
APLL
Backplane Data Memory
(4,096 channels)
Local Connection Memory
(2,432 locations)
Output
Mux
Local
Interface
P/S
Converter
HiZ
Control
Output
Mux
Local Data Memory
(2,432 channels)
Backplane Connection Memory
(4,096 locations)
Local
Interface
S/P
Converter
Local Interface
Timing Unit
DPLL
Internal Registers &
Microprocessor Interface
Test Port
STo0
STo27
LCSTo
STi0
STi27
ST_FPo0
ST_CKo0
ST_FPo1
ST_CKo1
Figure 1 - Functional Block Diagram
2
Zarlink Semiconductor Inc.

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