LTC1663 查看數據表（PDF） - Linear Technology

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LTC1663

10-Bit Rail-to-Rail Micropower DAC with 2-Wire Interface

Linear Technology 

PACKAGE DESCRIPTION

S5 Package

5-Lead Plastic TSOT-23

(Reference LTC DWG # 05-08-1635)

0.62

0.95

MAX

REF

1.22 REF

2.90 BSC

(NOTE 4)

3.85 MAX 2.62 REF

1.4 MIN

2.80 BSC

1.50 – 1.75

(NOTE 4)

LTC1663

RECOMMENDED SOLDER PAD LAYOUT

PER IPC CALCULATOR

0.20 BSC

DATUM ‘A’

0.30 – 0.50 REF

0.09 – 0.20

NOTE:

(NOTE 3)

1. DIMENSIONS ARE IN MILLIMETERS

2. DRAWING NOT TO SCALE

3. DIMENSIONS ARE INCLUSIVE OF PLATING

4. DIMENSIONS ARE EXCLUSIVE OF MOLD FLASH AND METAL BURR

5. MOLD FLASH SHALL NOT EXCEED 0.254mm

6. JEDEC PACKAGE REFERENCE IS MO-193

PIN ONE

0.95 BSC

0.80 – 0.90

1.00 MAX

1.90 BSC

0.30 – 0.45 TYP

5 PLCS (NOTE 3)

0.01 – 0.10

S5 TSOT-23 0302

0.889 ± 0.127

(.035 ± .005)

MS8 Package

8-Lead Plastic MSOP

(Reference LTC DWG # 05-08-1660)

3.00 ± 0.102

(.118 ± .004)

(NOTE 3)

8 7 65

5.23

(.206)

MIN

3.20 – 3.45

(.126 – .136)

0.254

(.010)

DETAIL “A”

0° – 6° TYP

4.90 ± 0.152

(.193 ± .006)

0.42 ± 0.038

(.0165 ± .0015)

TYP

0.65

(.0256)

BSC

RECOMMENDED SOLDER PAD LAYOUT

GAUGE PLANE

0.18

(.007)

0.53 ± 0.152

(.021 ± .006)

DETAIL “A”

1 234

1.10

(.043)

MAX

SEATING

NOTE:

PLANE

1. DIMENSIONS IN MILLIMETER/(INCH)

2. DRAWING NOT TO SCALE

3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.

MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE

4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.

INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE

5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX

0.22 – 0.38

(.009 – .015)

TYP

0.65

(.0256)

BSC

0.52

(.0205)

REF

3.00 ± 0.102

(.118 ± .004)

(NOTE 4)

0.86

(.034)

REF

0.127 ± 0.076

(.005 ± .003)

MSOP (MS8) 0204

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

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