MT9160AN1 查看數據表（PDF） - Zarlink Semiconductor Inc
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MT9160AN1 Datasheet PDF : 33 Pages
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MT91L60/61
Data Sheet
DEN - D-Channel
In ST-BUS mode access to the D-Channel (transmit and receive) data is provided through an 8-bit read/write
register (address 06h). D-Channel data is accumulated in, or transmitted from this register at the rate of 2 bits/frame
for 16 kb/s operation (1 bit/frame for 8 kb/s operation). Since the ST-BUS is asynchronous, with respect to the
microport, valid access to this register is controlled through the use of an interrupt (IRQ) output. D-Channel access
is enabled via the (DEn) bit.
DEN:
When 1, ST-BUS D-channel data (1 or 2 bits/frame depending on the state of the D8 bit) is shifted into/out of the D-
channel (READ/WRITE) register.
When 0, the receive D-channel data (READ) is still shifted into the proper register while the DSTo D-channel
timeslot and IRQ outputs are tri-stated (default).
D8:
When 1, D-Channel data is shifted at the rate of 1 bit/frame (8 kb/s).
When 0, D-Channel data is shifted at the rate of 2 bits/frame (16 kb/s default).
16 kb/s D-Channel operation is the default mode which allows the microprocessor access to a full byte of D-
Channel information every fourth ST-BUS frame. By arbitrarily assigning ST-BUS frame n as the reference frame,
during which the microprocessor D-Channel read and write operations are performed, then:
a. A microport read of address 04 hex will result in a byte of data being extracted which is composed of four
I-bits (designated by roman numerals I,II,III,IV). These di-bits are composed of the two D-Channel bits
received during each of frames n, n-1, n-2 and n-3. Referring to Fig. 7a: di-bit I is mapped from frame n-
3, di-bit II is mapped from frame n-2, di-bit III is mapped from frame n-1 and di-bit IV is mapped from
frame n.
The D-Channel read register is not preset to any particular value on power-up (PWRST) or software reset (RST).
b. A microport write to Address 04 hex will result in a byte of data being loaded which is composed of four
di-bits (designated by roman numerals I, II, III, IV). These di-bits are destined for the two D-Channel bits
transmitted during each of frames n+1, n+2, n+3, n+4. Referring to Fig. 7a: di-bit I is mapped to frame
n+1, di-bit II is mapped to frame n+2, di bit III is mapped to frame n+3 and di bit IV is mapped to frame
n+4.
If no new data is written to address 04 hex, the current D-channel register contents will be continuously re-
transmitted. The D-Channel write register is preset to all ones on power-up (PWRST) or software reset (RST).
An interrupt output is provided (IRQ) to synchronize microprocessor access to the D-Channel register during valid
ST-BUS periods only. IRQ will occur every fourth (eighth in 8 kb/s mode) ST-BUS frame at the beginning of the third
(second in 8 kb/s mode) ST-BUS bit cell period. The interrupt will be removed following a microprocessor Read or
Write of Address 04 hex or upon encountering the following frames F0i input, whichever occurs first. To ensure D-
Channel data integrity, microport read/write access to Address 04 hex must occur before the following frame pulse.
See Figure 7b for timing.
8 kb/s operation expands the interrupt to every eight frames and processes data one-bit-per-frame. D-Channel
register data is mapped according to Figure 7c.
CEn - C-Channel
Channel 1 conveys the control/status information for the Layer 1 transceiver. C-Channel data is transferred MSB
first on the ST-BUS by the MT91L60/61. The full 64 kb/s bandwidth is available and is assigned according to which
transceiver is being used. Consult the data sheet for the selected transceiver for its C-Channel bit definitions and
order of bit transfer.
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