MT9160AN1 查看數據表（PDF） - Zarlink Semiconductor Inc

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MT9160AN1

ISO2-CMOS 3 Volt Multi-Featured Codec (MFC)

Zarlink Semiconductor Inc 

MT91L60/61

Data Sheet

COMMAND/ADDRESS 5) 1)

DATA INPUT/OUTPUT

1)

4) COMMAND/ADDRESS:

DATA 1

RECEIVE

D0

D1

D2

D3

D4

D5

D6

D7

D0 D1 D2 D3 D4 D5 D6 D7

D0 D1 D2 D3 D4 D5 D6 D7

DATA 1

TRANSMIT

SCLK 2)

D0 D1 D2 D3 D4 D5 D6 D7

D0 D1 D2 D3 D4 D5 D6 D7

CS

4)

3)

3)

1) Delays due to internal processor timing which are transparent.

2) The MT91L60/L61:latches received data on the rising edge of SCLK.

-outputs transmit data on the falling edge of SCLK.

3) The falling edge of CS indicates that a COMMAND/ADDRESS byte will be transmitted from the microprocessor. The

subsequent byte is always data until terminated via CS returning high.

4) A new COMMAND/ADDRESS byte may be loaded only by CS cycling high then low again.

5) The COMMAND/ADDRESS byte contains: 1 bit - Read/Write

D7

D0

3 bits - Addressing Data

4 bits - Unused

XX

X

X A2 A1 A0 R/W

Figure 4 - Audio Gain Partitioning

COMMAND/ADDRESS 5) 1)

DATA INPUT/OUTPUT

1)

4) COMMAND/ADDRESS:

DATA 2

RECEIVE

D7

D6

D5

D4

D3

D2

D1

D0

D7 D6 D5 D4 D3 D2 D1 D0

D7 D6 D5 D4 D3 D2 D1 D0

DATA 1

TRANSMIT

SCLK 2)

D7 D6 D5 D4 D3 D2 D1 D0

D7 D6 D5 D4 D3 D2 D1 D0

CS

4)

3)

3)

1) Delays due to internal processor timing which are transparent.

2) The MT91L60/L61: latches received data on the rising edge of SCLK.

-outputs transmit data on the falling edge of SCLK.

3) The falling edge of CS indicates that a COMMAND/ADDRESS byte will be transmitted from the microprocessor. The

subsequent byte is always data until terminated via CS returning high.

4) A new COMMAND/ADDRESS byte may be loaded only by CS cycling high then low again.

5) The COMMAND/ADDRESS byte contains:

1 bit - Read/Write

3 bits - Addressing Data

4 bits - Unused

D7

R/W X X

D0

X A2 A1 A0 X

Figure 5 - Serial Port Relative Timing for Motorola Mode 00/National Microwire

8

Zarlink Semiconductor Inc.

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