CY7C4804V25 查看數據表（PDF） - Cypress Semiconductor

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CY7C4804V25

2.5V 4K/16K/64K x 80 Unidirectional Synchronous FIFO w/Bus Matching

Cypress Semiconductor 

CY7C4808V25

sure

0251

CY7C4806V25

PRELIMINARY

CY7C4804V25

2.5V 4K/16K/64K x 80 Unidirectional

Synchronous FIFO w/Bus Matching

Features

• High-speed, low-power, unidirectional, first-in first-out

(FIFO) memories w/bus matching capabilities

• 64K x 80 (CY7C4808V25)

• 16K x 80 (CY7C4806V25)

• 4K x 80 (CY7C4804V25)

• 2.5V ± 100 mV power supply

• All I/Os are 1.5V HSTL

• Individual clock frequency up to 200 MHz (5 ns

read/write cycle times)

• High-speed access with tA = 3.3 ns

• Bus matching on both ports: x80, x40, x20, x10

• Free-running CLKA and CLKB. Clocks may be asyn-

chronous or coincident

• CY standard or First-Word Fall-Through modes

• Serial and parallel programming of Almost Empty/Full

flags, each with 3 default values (8, 16, 64)

• Master and Partial reset capability

• Retransmit capability

• Big or Little Endian format on Port B

• 288 FBGA 19 mm x 19 mm (1.0-mm ball pitch) packaging

• Width and depth expansion capability

• Fabricated using Cypress 0.21-micron CMOS Technol-

ogy for optimum speed/power

Preliminary Top Level Block Diagram

CLKA

CSA

ENA

SIZE1A

SIZE2A

Port A

Control

Logic

80

A79–0

4K/16K/64Kx80

Memory

Dual Ported

Port B

Control

Logic

CLKB

CSB

ENB

BE/FWFT

SIZE1B

SIZE2B

RT/SPM

OE

80

B79–0

MR

FIFO

Reset

PR

Logic

FF/IR

AF

FS0/SD

FS1/SEN

Write

Pointer

Read

Pointer

Status

Flag Logic

Programmable Flag Offset Registers

TDO

EF/OR

AE

JTAG Controller

TDI TCK TMS TRST

For the most recent information, visit the Cypress web site at www.cypress.com

Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600

July 18, 2000

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