MSM5718C50 查看數據表（PDF） - Oki Electric Industry
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MSM5718C50 Datasheet PDF : 46 Pages
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¡ Semiconductor
MSM5718C50/MD5764802
In this example, three additional octbytes are read from the activated page. These column addresses
(COLb, COLc, and COLd) are transferred in T3, T4, and T5, respectively. The data octbytes (DOUTb,
DOUTc, and DOUTd) are transferred in T6, T7, and T8, The end of the data octbytes is signaled by
a third command RTERM (read terminate) in T6. The next REQ packet may be sent in T9, or in any
interval thereafter.
Figure 4 (b) shows an example of a write transaction. The transaction begins in interval T0 with the
transfer of a REQ packet. The REQ packet contains, the command (ACTV/WRITE), a device, bank,
and row address (BNK/ROW) of the page to be activated, and the column address (COLa) of the first
octbyte to be written to the page.
The selected bank performs the activation of the selected row during T1 and T2 (the tRCD interval).
A second command WSTRB (write strobe) is transferred during T2 and causes the first octbyte
(DINa) to be transferred during T3.
In this example, three additional octbytes are written to the activated page. These column addresses
(COLb, COLc, and COLd) are transferred in T2, T3, and T4 respectively. The data octbytes (DINb,
DINc, and DINd) are transferred in T4, T5, and T6. The end of the data octbytes is signaled by a third
command WTERM (write termination) in T6. The next REQ packet may be sent in T7, or in any
interval thereafter.
INTERLEAVED TRANSACTIONS
The previous examples showed noninterleaved transactions - the next REQ packet was transferred
after the last data octbyte of the current transaction. In an interleaved transaction, the next REQ packet
is transferred before the first data octbyte of the current transaction. This permits the row and column
access intervals of the next transaction to overlap the data transfer of the current transaction.
Figure 5 shows an example of interleaved read transactions. The first transaction proceeds exactly
as the noninterleaved example of Figure 4 (a) (all packets of the first transaction are labeled with “1”).
However, in T5 the REQ packet for the second transaction is transferred (all packets of the second
transaction are labeled with “2”). The tRCD2 and tCAC2 intervals overlap the transfer of DOUT1 data
octbytes and thus increase the effective bandwidth of the RDRAM since there are no unused
intervals.
A transaction consists of an address transfer phase and a data transfer phase. The REQ packet
performs address transfer, and the remaining packets perform data transfer (DOUT, COL, RSTRB,
and RTERM in the case of a read transaction). The time interval between the address and data transfer
phases of the current transaction may be adjusted to match the data length of the previous transaction
(as long as the row and column access times for the current transaction are observed). Thus, there are
no limits on the types of memory transaction which may be interleaved; any mixing of transaction
length and command type is permitted.
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