HYB39S64160AT 查看數據表（PDF） - Infineon Technologies
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HYB39S64160AT Datasheet PDF : 53 Pages
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HYB39S64400/800/160AT(L)
64MBit Synchronous DRAM
Column address
counter
Column Addresses
A0 - A9, AP, BA0, BA1
Column address
buffer
Row Addresses
A0 - A11, BA0, BA1
Row address
buffer
Row decoder
Memory array
Bank 0
4096 x 1024
x 4 bit
Row decoder
Memory array
Bank 1
4096 x 1024
x 4 bit
Row decoder
Memory array
Bank 2
4096 x 1024
x 4 bit
Refresh Counter
Row decoder
Memory array
Bank 3
4096 x 1024
x 4 bit
Input buffer Output buffer
DQ0-DQ3
Control logic & timing generator
Block Diagram for 4 bank x 4M x 4 SDRAM
Semiconductor Group
4
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