VSC6464 查看數據表（PDF） - Vitesse Semiconductor
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VSC6464 Datasheet PDF : 10 Pages
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VITESSE
SEMICONDUCTOR CORPORATION
64x64 Crosspoint Switch
Advance Product Information
VSC6464
Functional Description
This Crosspoint Switch connects any of the 64 inputs to any combination of 64 output channels, according
to a user defined bit pattern stored in each channel’s control register.
Signals from the 64 inputs (DIN_0 through DIN_63) are connected to the 64 output channels (DOUT_0
through DOUT_63) through sixty-four 64:1 multiplexers. The traffic pattern is controllable by data stored in
sixty-four 6-bit control registers with each register corresponding to an output channel. The six bits are a binary
numerical representation of the input channel selected (i.e.: 000000 corresponds to DIN_0, 000001 corresponds
to DIN_1, etc.). An additional six bit register is used to address the output channel being programmed. These six
bits are a binary numerical representation of the output channel (ie.: 000000 corresponds to DOUT_0, 000001
corresponds to DOUT_1, etc.). All twelve configuration bits are loaded through a three-pin serial port.
The crosspoint is configured through a serial data port consisting of three pins: SERS, SERC, and SERD.
SERS is used to select the crosspoint for configuration. SERC is a serial clock signal whose rising edge samples
the serial data on SERD when SERS is active (HI). The serial data stream applied to SERD consists of the six
bits of address, followed by the six bits of data. Address information is used to identify one of the 64 output
channels, a valid value is between 0 and 63. Data information selects a specific input to be directed to the
addressed output, valid values are between 0 and 63. Both address and data information are received MSB first.
A serial load cycle consists of activating serial select (SERS), pulsing serial clock 12 times (with valid data sur-
rounding each rising edge), then deactivating serial select (SERS). Deactivating serial select before the twelfth
rising edge of SERC will abort the load cycle. Serial select (SERS) must be deactivated for 10ns following a
power up. Any additional clocking of SERC during a load cycle, beyond that described above, is ignored.
The MODE pin determines the operating mode of the Crosspoint: synchronous or asynchronous, as shown
in Table 1.
A test output (TESTO) is provided for internal visibility, this signal will go high when a thirteenth rising
edge is applied during a load cycle; TESTO goes low when either SERS is lowered, or a fourteenth SERC edge
is received during a load cycle. This output can be left unconnected if desired, to reduce noise and power dissi-
pation.
Table 1: Crosspoint Mode (MODE)
Function
Asynchronous 64x64
Synchronous 64x64
MODE
0
1
Page 2
© VITESSE SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
G52219-0, Rev. 2.0
8/4/98
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