MX844R 查看數據表（PDF） - IXYS CORPORATION
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MX844R Datasheet PDF : 21 Pages
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MX844
IXYS
Example internal divider settings and clock frequencies for standard baud rates:
CR7:5 M1
Baud
divider
ADC
divider
Clock baud ADC
Clock baud ADC
(MHz) rate conv/s (MHz) rate conv/s
000 1
8*52
8
001 1
4*52
4
010 1
12*64
12
011 1
13*64
13
12.0 28.8K 366
6.0 28.8K 366
11.059 14.4K 225
12.0 14.4K 225
16.0 38.4K 488
8.0 38.4K 488
14.746 19.2K 300
16.0 19.2K 300
000 0
8*64
8
001 0
4*64
4
010 0
6*64
6
011 0
3*64
3
14.746 28.8K 450
14.746 57.6K 900
11.059 28.8K 450
11.059 57.6K 900
9.83 19.2K 300
9.83 38.4K 600
14.746 38.4K 600
7.37 38.4K 600
100 1
101 1
110 1
111 1
8*128 8*4*5
9.83 9600 15
9*128 9*4*5
11.059 9600 15
12*128 12*4*5 14.746 9600 15
13*128 13*4*5 16.0 9600 15
100 0
101 0
110 0
111 0
8*128 8*4*6
9.83 9600 12.5
9*128 9*4*6
11.059 9600 12.5
12*128 12*4*6 14.746 9600 12.5
13*128 13*4*6 16.0 9600 12.5
SYNCHRONOUS SERIAL I/O
The MX844 (slave) can communicate with a microcomputer (master) via a three wire plus chip select
serial interface. The control register, the two digital comparator values, and the ADC result are accessed
by specifying a 3-bit address A[2:0]. Chip select CS, serial clock SCK, and serial data input SDI are
output from the master controller to the MX844. Serial data output SDO is driven by the MX844 when
selected by CS = 0. SDO is high impedance when CS = 1. SCK and SDI are don't care when CS = 1.
SERIAL INTERFACE TIMING
READ:
CS
1.5 * tClock min
SCK
SDI
RW = 0
A2 A1 A0
tClock = the period of the X1 input clock
SDO
WRITE:
SDI
1.2 * tClock min
RW = 1
B7 B6 B5 B4 B3 B2 B1 B0
2 * tClock max
A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 B0
SCK minimum high or low time is 3 * tClock.
SDO is high impedance until data read out, and then returns to high impedance due to the rising edge of CS.
MX844
Drawing No. 084423
7
08/25/06
www.claremicronix.com
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