NB100LVEP221FARG 查看數據表（PDF） - ON Semiconductor

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NB100LVEP221FARG

2.5V/3.3V1:20 Differential HSTL/ECL/PECL Clock Driver

ON Semiconductor 

NB100LVEP221

2.5V/3.3V 1:20 Differential

HSTL/ECL/PECL Clock Driver

Description

The NB100LVEP221 is a low skew 1−to−20 differential clock

driver, designed with clock distribution in mind, accepting two clock

sources into an input multiplexer. The two clock inputs are differential

ECL/PECL; CLK1/CLK1 can also receive HSTL signal levels. The

LVPECL input signals can be either differential configuration or

single−ended (if the VBB output is used).

The LVEP221 specifically guarantees low output−to−output skew.

Optimal design, layout, and processing minimize skew within a device

and from device to device.

To ensure tightest skew, both sides of differential outputs should be

terminated identically into 50 W even if only one output is being used.

If an output pair is unused, both outputs may be left open

(unterminated) without affecting skew.

The NB100LVEP221, as with most other ECL devices, can be

operated from a positive VCC supply in LVPECL mode. This allows the

LVEP221 to be used for high performance clock distribution in +3.3 V or

+2.5 V systems. In a PECL environment, series or Thevenin line

terminations are typically used as they require no additional power

supplies. For more information on PECL terminations, designers should

refer to Application Note AND8020/D.

The VBB pin, an internally generated voltage supply, is available to this

device only. For single−ended LVPECL input conditions, the unused

differential input is connected to VBB as a switching reference voltage.

VBB may also rebias AC coupled inputs. When used, decouple VBB and

VCC via a 0.01 mF capacitor and limit current sourcing or sinking to

0.5 mA. When not used, VBB should be left open.

Single−ended CLK input operation is limited to a VCC ≥ 3.0 V in

LVPECL mode, or VEE ≤ −3.0 V in NECL mode.

Features

• 15 ps Typical Output−to−Output Skew

• 40 ps Typical Device−to−Device Skew

• Jitter Less than 2 ps RMS

• Maximum Frequency > 1.0 GHz Typical

• Thermally Enhanced 52−Lead LQFP

• VBB Output

• 540 ps Typical Propagation Delay

• LVPECL and HSTL Mode Operating Range:

VCC = 2.375 V to 3.8 V with VEE = 0 V

• NECL Mode Operating Range:

VCC = 0 V with VEE = −2.375 V to −3.8 V

• Q Output will Default Low with Inputs Open or at VEE

• Pin Compatible with Motorola MC100EP221

• Pb−Free Packages are Available*

*For additional information on our Pb−Free strategy and soldering details, please

download the ON Semiconductor Soldering and Mounting Techniques

Reference Manual, SOLDERRM/D.

© Semiconductor Components Industries, LLC, 2006

1

November, 2006 − Rev. 7

http://onsemi.com

MARKING

DIAGRAM*

LQFP−52

FA SUFFIX

CASE 848H

NB100

LVEP221

AWLYYWWG

52

1

A

= Assembly Location

WL = Wafer Lot

YY

= Year

WW = Work Week

G

= Pb−Free Package

*For additional marking information, refer to

Application Note AND8002/D.

ORDERING INFORMATION

See detailed ordering and shipping information in the package

dimensions section on page 9 of this data sheet.

Publication Order Number:

NB100LVEP221/D

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