NB2304AI1HDR2G 查看數據表（PDF） - ON Semiconductor

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NB2304AI1HDR2G

3.3 V Zero Delay Clock Buffer

ON Semiconductor 

NB2304A

3.3 V Zero Delay

Clock Buffer

The NB2304A is a versatile, 3.3 V zero delay buffer designed to

distribute high−speed clocks in PC, workstation, datacom, telecom

and other high−performance applications. It is available in an 8 pin

package. The part has an on−chip PLL which locks to an input clock

presented on the REF pin. The PLL feedback is required to be driven

to FBK pin, and can be obtained from one of the outputs. The

input−to−output propagation delay is guaranteed to be less than

250 ps, and the output−to−output skew is guaranteed to be less than

200 ps.

The NB2304A has two Banks of two outputs each. Multiple

NB2304A devices can accept the same input clock and distribute it. In

this case, the skew between the outputs of the two devices is

guaranteed to be less than 500 ps.

The NB2304A is available in two different configurations (Refer to

NB2304A Configurations Table). The NB2304Ax1* is the base part,

where the output frequencies equal the reference if there is no counter

in the feedback path. The NB2304Ax1H is the high−drive version of

the −1 and the rise and fall times on this device are much faster.

The NB2304Ax2 allows the user to obtain REF, 1/2 X and 2X

frequencies on each output Bank. The exact configuration and output

frequencies depend on which output drives the feedback pin.

Features

• Zero Input − Output Propagation Delay, Adjustable by Capacitive

Load on FBK Input

• Multiple Configurations − Refer to NB2304A Configurations Table

• Input Frequency Range: 15 MHz to 133 MHz

• Multiple Low−Skew Outputs

• Output−Output Skew < 200 ps

• Device−Device Skew < 500 ps

• Two Banks of Four Outputs

• Less than 200 ps Cycle−to−Cycle Jitter (−1, −1H, −5H)

• Available in Space Saving, 8 pin 150 mil SOIC Package

• 3.3 V Operation

• Advanced 0.35 m CMOS Technology

• Industrial Temperature Available

• These are Pb−Free Devices

http://onsemi.com

8

1

SOIC−8

D SUFFIX

CASE 751

MARKING

DIAGRAM*

8

XXXX

ALYW

G

1

XXXX = Device Code

A = Assembly Location

L = Wafer Lot

Y = Year

W = Work Week

G = Pb−Free Package

*For additional marking information, refer to

Application Note AND8002/D.

ORDERING INFORMATION

See detailed ordering and shipping information in the package

dimensions section on page 9 of this data sheet.

*x = C for Commercial; I for Industrial.

© Semiconductor Components Industries, LLC, 2006

1

November, 2006 − Rev. 5

Publication Order Number:

NB2304A/D

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