NB2304AC2DG 查看數據表（PDF） - ON Semiconductor
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NB2304AC2DG Datasheet PDF : 10 Pages
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NB2304A
Table 6. SWITCHING CHARACTERISTICS FOR COMMERCIAL TEMPERATURE DEVICES
Parameter
Description
Test Conditions
Min Typ Max
t1
Output Frequency
30 pF load (all devices)
15 pF load (−1, −2)
15
133
15
133.3
Duty Cycle = (t2 / t1) * 100
(all devices)
Measured at 1.4 V, FOUT = 66.66 MHz
30 pF load
Measured at 1.4 V, FOUT v 50 MHz
15 pF load
40.0 50.0 60.0
45.0 50.0 55.0
t3
Output Rise Time
Measured between 0.8 V and 2.0 V
2.20
(−1, −2)
30 pF load
Measured between 0.8 V and 2.0 V
1.50
15 pF load
Output Rise Time
Measured between 0.8 V and 2.0 V
1.50
(−1H)
30 pF load
t4
Output Fall Time
Measured between 2.0 V and 0.8 V
2.20
(−1, −2)
30 pF load
Measured between 2.0 V and 0.8 V
1.50
15 pF load
Output Fall Time
Measured between 2.0 V and 0.8 V
1.25
(−1H)
30 pF load
t5
Output−to−Output Skew on same Bank All outputs equally loaded
200
(−1, −2)
Output−to−Output Skew
All outputs equally loaded
200
(−1H)
Output Bank A−to−Output Bank B Skew All outputs equally loaded
200
(−1)
Output Bank A−to−Output Bank B Skew All outputs equally loaded
400
(−2)
t6
Delay, REF Rising Edge to FBK Rising Measured at VDD/2
Edge
0 ±250
t7
Device−to−Device Skew
Measured at VDD/2 on the FBK pins of the
device
0 500
t8
Output Slew Rate
Measured between 0.8 V and 2.0 V using
1
Test Circuit #2
tJ
Cycle−to−Cycle Jitter
Measured at 66.67 MHz, loaded outputs,
175
(−1, −1H)
15 pF load
Measured at 66.67 MHz, loaded outputs,
200
30 pF load
Measured at 133.3 MHz, loaded outputs,
100
15 pF load
Cycle−to−Cycle Jitter
Measured at 66.67 MHz, loaded outputs,
400
(−2)
30 pF load
Measured at 66.67 MHz, loaded outputs,
375
15 pF load
tLOCK
PLL Lock Time
Stable power supply, valid clock presented
1.0
on REF and FBK pins
Unit
MHz
%
ns
ns
ps
ps
ps
V/ns
ps
ps
ms
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