NB2308AI2DTG 查看數據表（PDF） - ON Semiconductor

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NB2308AI2DTG

3.3 V Zero Delay Clock Buffer

ON Semiconductor 

REF 1

CLKA1 2

CLKA2 3

VDD 4

GND 5

CLKB1 6

CLKB2 7

S2 8

NB2308A

NB2308A

16 FBK

15 CLKA4

14 CLKA3

13 VDD

12 GND

11 CLKB4

10 CLKB3

9 S1

Figure 2. Pin Configuration

Table 3. PIN DESCRIPTION

Pin #

Pin Name

1

REF (Note 3)

2

CLKA1 (Note 4)

3

CLKA2 (Note 4)

4

VDD

5

GND

6

CLKB1 (Note 4)

7

CLKB2 (Note 4)

8

S2 (Note 5)

9

S1 (Note 5)

10

CLKB3 (Note 4)

11

CLKB4 (Note 4)

12

GND

13

VDD

14

CLKA3 (Note 4)

15

CLKA4 (Note 4)

16

FBK

3. Weak pulldown.

4. Weak pulldown on all outputs.

5. Weak pullup on these inputs.

Description

Input reference frequency, 5 V tolerant input.

Buffered clock output, Bank A.

Buffered clock output, Bank A.

3.3 V supply.

Ground.

Buffered clock output, Bank B.

Buffered clock output, Bank B.

Select input, bit 2.

Select input, bit 1.

Buffered clock output, Bank B.

Buffered clock output, Bank B.

Ground.

3.3 V supply.

Buffered clock output, Bank A.

Buffered clock output, Bank A.

PLL feedback input.

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