NCP1378DR2 查看數據表（PDF） - ON Semiconductor

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NCP1378DR2

PWM Current−Mode Controller for Free−Running Quasi−Resonant Operation

ON Semiconductor 

Drain

Signal

NCP1378

Timeout

Signal

Drain

Signal

Demag RESTART

Current Sense and Timeout Restart

Timeout

Signal

5 ms

5 ms

Figure 19. When the primary natural ringing becomes too low, the current

sense initiates a new cycle when FB passes the skip level.

Demagnetization Detection

The core reset detection is done by monitoring the

voltage activity on the auxiliary winding. This voltage

features a FLYBACK polarity. The typical detection level

is fixed at 50 mV as exemplified by Figure 20.

7.0

5.0

POSSIBLE

RESTARTS

3.0

1.0

0V

−1.0

50 mV

TO INTERNAL

COMPARATOR

Resd

2k

3

ESD

1

4

ESD

Rdem

5

2

Aux

4

1

Figure 20. Core Reset Detection is Done through

a Dedicated Auxiliary Winding Monitoring

An internal timer prevents any restart within 8.0 ms

further to the driver going−low transition. This prevents the

switching frequency to exceed (1.0/TON + 8.0 ms) but also

Figure 21. Internal Pad Implementation

avoid false leakage inductance tripping at turn−off. In some

cases, the leakage inductance kick is so energetic, that a

slight filtering is necessary.

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