NCP1250 查看數據表（PDF） - ON Semiconductor
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NCP1250 Datasheet PDF : 23 Pages
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OPP
Vlatch
vdd
NCP1250
OVP
gone?
600−ns time
constant
Up counter
RST
4
Vcc and logic
management
vdd
power
on reset
hiccup
IpFlag
UVLO
S
Q
Q
Frequency
modulation
R
Power on
reset
1−us
blanking
65
100 kHz
clock
Vfold
Frequency
foldback
S
Q
Q
R
Rlim
Iscr
Clamp
Vskip
vdd
RFB
FB
/ 4.2
CS
LEB
Rramp
The soft−start is activated during:
− the startup sequence
− the auto−recovery burst mode
4 ms
SS
IpFlag
250 mV
peak current
freeze
VOPP
VFB < 1.05 V ? setpoint = 250 mV
+ Vlimit + VOPP
Vlimit
Figure 2. Internal Circuit Architecture
Vcc
Drv
GND
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