NCV4290(2012) 查看數據表（PDF） - ON Semiconductor

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NCV4290
(Rev.:2012)

5.0 V, 450 mA Low-Dropout Voltage Regulator with Power Good

ON Semiconductor 

NCV4290

APPLICATION INFORMATION

VI

II

CI1

CI2

I1

5Q

IQ

CQ

VQ

1000 mF

100 nF

NCV4290

22 mF

Rext

5.0 k

ID

CD

D4

3

2 PG

IPG

VPG

47 nF

GND

Iq

Figure 13. Test Circuit

Circuit Description

The NCV4290 is an integrated low dropout regulator that

provides 5.0 V, 450 mA protected output and a signal for

power on power good. The regulation is provided by a PNP

pass transistor controlled by an error amplifier with a bandgap

reference, which gives it the lowest possible drop out voltage

and best possible temperature stability. The output current

capability is 450 mA, and the base drive quiescent current is

controlled to prevent over saturation when the input voltage

is low or when the output is overloaded. The regulator is

protected by both current limit and thermal shutdown.

Thermal shutdown occurs above 150°C to protect the IC

during overloads and extreme ambient temperatures. The

delay time for the power good output is adjustable by

selection of the timing capacitor. See Figure 13, Test Circuit,

for circuit element nomenclature illustration.

Regulator

The error amplifier compares the reference voltage to a

sample of the output voltage (VQ) and drives the base of a

PNP series pass transistor by a buffer. The reference is a

bandgap design to give it a temperature−stable output.

Saturation control of the PNP is a function of the load

current and input voltage. Over saturation of the output

power device is prevented, and quiescent current in the

ground pin is minimized.

Regulator Stability Considerations

The input capacitors (CI1 and CI2) are necessary to

stabilize the input impedance to avoid voltage line

influences. Using a resistor of approximately 1.0 W in

series with CI2 can stop potential oscillations caused by

stray inductance and capacitance.

The output capacitor helps determine three main

characteristics of a linear regulator: startup delay, load

transient response and loop stability. The capacitor value

and type should be based on cost, availability, size and

temperature constraints. A tantalum, aluminum or ceramic

capacitors can be used. The range of stability versus

capacitance, load current and capacitive ESR is illustrated

in Figures 2 and 3. Minimum ESR for CQ = 22 mF is native

ESR of ceramic capacitors. The aluminum electrolytic

capacitor is the least expensive solution, but, if the circuit

operates at low temperatures (−25°C to −40°C), both the

capacitance and ESR of the capacitor will vary considerably.

The capacitor manufacturer’s data sheet usually provides this

information.

The value for the output capacitor CQ shown in

Figure 13, Test Circuit, should work for most applications;

however, it is not necessarily the optimized solution.

Stability is guaranteed for CQ ≥ 22 mF and an ESR ≤ 4.0 W.

ESR characteristics were measured with ceramic

capacitors and additional resistors to emulate ESR. Murata

ceramic capacitors were used, GRM32ER71C226ME18

(22 mF, 16 V, X7R, 1210), GRM219R71E105KA88 (1 mF,

25 V, X7R, 0805).

Power Good Output

The power good output is used as the power on indicator

to the microcontroller. This signal indicates when the

output voltage is suitable for reliable operation of the

controller. It pulls low when the output is not considered to

be ready. PG is pulled up to VQ by an external resistor,

typically 5.0 kW in value. Hysteresis is implemented for

PG signal. When output voltage is decreasing PG goes

Low at VQ typ 3.65 V and when output voltage is

increasing PG goes High at VQ typ 4.65 V. The input and

output conditions that control the Power Good Output and

the relative timing are illustrated in Figure 14, Power Good

Timing.

Output voltage regulation must be maintained for the delay

time before the power good output signals a valid condition.

The delay for the power good output is defined as the amount

of time it takes the timing capacitor on the delay pin to charge

from a residual voltage of 0.0 V to the upper timing threshold

voltage VDU. The charging current for this is ID,C and D pin

voltage in steady state is typically 2.85 V. By using typical IC

parameters with a 47 nF capacitor on the D pin, the following

time delay for 5.0 V regulator is derived:

tRD = CDVDU / ID,C

tRD = 47 nF (1.8 V) / 6.0 mA = 14.1 ms

Other time delays can be obtained by changing the

capacitor value.

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