NCV7356 查看數據表（PDF） - ON Semiconductor

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NCV7356

Single Wire CAN Transceiver

ON Semiconductor 

NCV7356

FUNCTIONAL DESCRIPTION

TxD Input Pin

TxD Polarity

• TxD = logic 1 (or floating) on this pin produces an

undriven or recessive bus state (low bus voltage)

• TxD = logic 0 on this pin produces either a bus normal

or a bus high voltage dominant state depending on the

transceiver mode state (high bus voltage)

If the TxD pin is driven to a logic low state while the sleep

mode (Mode 0 = 0 and Mode 1 = 0) is activated, the

transceiver can not drive the CANH pin to the dominant

state.

The transceiver provides an internal pullup current on the

TxD pin which will cause the transmitter to default to the

bus recessive state when TxD is not driven.

TxD input signals are standard CMOS logic levels.

Timeout Feature

In case of a faulty blocked dominant TxD input signal,

the CANH output is switched off automatically after the

specified TxD timeout reaction time to prevent a dominant

bus.

The transmission is continued by next TxD L to H

transition without delay.

MODE0 and MODE1 Pins

The transceiver provides a weak internal pulldown

current on each of these pins which causes the transceiver

to default to sleep mode when they are not driven. The

mode input signals are standard CMOS logic level for

3.3 V and 5 V supply voltages.

MODE0

L

H

L

H

MODE1

L

L

H

H

Mode

Sleep Mode

High−Speed Mode

High Voltage Wake−Up

Normal Mode

Sleep Mode

Transceiver is in low power state, waiting for wake−up

via high voltage signal or by mode pins change to any state

other than 0,0. In this state, the CANH pin is not in the

dominant state regardless of the state of the TxD pin.

High−Speed Mode

This mode allows high−speed download with bit rates up

to 100 Kbit/s. The output wave shapingaping circuit is

disabled in this mode. Bus transmitter drive circuits for

those nodes which are required to communicate in

high−speed mode are able to drive reduced bus resistance

in this mode.

High Voltage Wake−Up Mode

This bus includes a selective node awake capability,

which allows normal communication to take place among

some nodes while leaving the other nodes in an undisturbed

sleep state. This is accomplished by controlling the signal

voltages such that all nodes must wake−up when they

receive a higher voltage message signal waveform. The

communication system communicates to the nodes

information as to which nodes are to stay operational

(awake) and which nodes are to put themselves into a non

communicating low power “sleep” state. Communication

at the lower, normal voltage levels shall not disturb the

sleeping nodes.

Normal Mode

Transmission bit rate in normal communication is

33 Kbits/s. In normal transmission mode the NCV7356

supports controlled waveform rise and overshoot times.

Waveform trailing edge control is required to assure that

high frequency components are minimized at the

beginning of the downward voltage slope. The remaining

fall time occurs after the bus is inactive with drivers off and

is determined by the RC time constant of the total bus load.

RxD Output Pin

Logic data as sensed on the single wire CAN bus.

RxD Polarity

• RxD = logic 1 on this pin indicates a bus recessive

state (low bus voltage)

• RxD = logic 0 on this pin indicates a bus normal or

high voltage bus dominant state

RxD in Sleep Mode

RxD does not pass signals to the microprocessor while in

sleep mode until a valid wake−up bus voltage level is

received or the MODE0 and MODE 1 pins are not 0, 0

respectively. When the valid wake−up bus voltage signal

awakens the transceiver, the RxD pin signals an interrupt

(logic 0). If there is no mode change within 250 ms (typ),

the transceiver re−enters the sleep mode.

When not in sleep mode all valid bus signals will be sent

out on the RxD pin.

RxD will be placed in the undriven or off state when in

sleep mode.

RxD Typical Load

Resistance: 2.7 kW

Capacitance: < 25 pF

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